@@ -5742,16 +5742,16 @@ (define_insn_and_split "fixuns_trunc<mod
(set_attr "type" "fp")])
(define_expand "fixuns_trunc<mode>di2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ "TARGET_HARD_FLOAT && ((TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCTIDUZ)
+ || VECTOR_UNIT_VSX_P (<MODE>mode))"
"")
(define_insn "*fixuns_trunc<mode>di2_fctiduz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
- && TARGET_FCTIDUZ"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCTIDUZ"
"@
fctiduz %0,%1
xscvdpuxds %x0,%x1"
@@ -1650,7 +1650,7 @@ (define_insn "vsx_fix_trunc<mode><VSi>2"
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
- (unsigned_fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
+ (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")
@@ -0,0 +1,11 @@
+/* PR target/79197 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mno-popcntd" } */
+
+unsigned a;
+
+void
+foo (void)
+{
+ a = *(double *) (__UINTPTR_TYPE__) 0x400000;
+}
@@ -0,0 +1,10 @@
+/* PR target/79197 */
+
+unsigned long b;
+
+unsigned long
+foo (float *a, float *x)
+{
+ __builtin_memcpy (a, x, sizeof (float));
+ return *a;
+}