From patchwork Thu Nov 18 08:46:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 72066 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E5F2CB7170 for ; Thu, 18 Nov 2010 19:47:15 +1100 (EST) Received: from localhost ([127.0.0.1]:33559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJ09A-0003jH-73 for incoming@patchwork.ozlabs.org; Thu, 18 Nov 2010 03:47:12 -0500 Received: from [140.186.70.92] (port=52524 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJ08d-0003jC-Nx for qemu-devel@nongnu.org; Thu, 18 Nov 2010 03:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PJ08c-0003IF-EV for qemu-devel@nongnu.org; Thu, 18 Nov 2010 03:46:39 -0500 Received: from mx1.redhat.com ([209.132.183.28]:54408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PJ08c-0003I9-3N for qemu-devel@nongnu.org; Thu, 18 Nov 2010 03:46:38 -0500 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAI8kaJk012810 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 18 Nov 2010 03:46:36 -0500 Received: from redhat.com (vpn-8-4.rdu.redhat.com [10.11.8.4]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id oAI8kWHD029638; Thu, 18 Nov 2010 03:46:33 -0500 Date: Thu, 18 Nov 2010 10:46:25 +0200 From: "Michael S. Tsirkin" To: Isaku Yamahata Message-ID: <20101118084625.GA16832@redhat.com> References: <48f736e1a86a0db8ad368a42103d4e366a2dbd22.1289969012.git.yamahata@valinux.co.jp> <20101118070530.GB15274@redhat.com> <20101118072910.GR18102@valinux.co.jp> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20101118072910.GR18102@valinux.co.jp> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: skandasa@cisco.com, Anthony Liguori , etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com Subject: [Qemu-devel] Re: [PATCH 7/7] pci bridge: implement secondary bus reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Thu, Nov 18, 2010 at 04:29:10PM +0900, Isaku Yamahata wrote: > On Thu, Nov 18, 2010 at 09:05:30AM +0200, Michael S. Tsirkin wrote: > > On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote: > > > Emulates secondary bus reset when secondary bus reset bit > > > is written from 0 to 1. > > > > > > Signed-off-by: Isaku Yamahata > > > Signed-off-by: Anthony Liguori > > > --- > > > hw/pci_bridge.c | 12 +++++++++++- > > > 1 files changed, 11 insertions(+), 1 deletions(-) > > > > > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > > > index 58cc2e4..618a81e 100644 > > > --- a/hw/pci_bridge.c > > > +++ b/hw/pci_bridge.c > > > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) > > > void pci_bridge_write_config(PCIDevice *d, > > > uint32_t address, uint32_t val, int len) > > > { > > > + PCIBridge *s = container_of(d, PCIBridge, dev); > > > + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > > > + uint16_t bridge_control_new; > > > + > > > pci_default_write_config(d, address, val, len); > > > > > > if (/* io base/limit */ > > > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, > > > /* memory base/limit, prefetchable base/limit and > > > io base/limit upper 16 */ > > > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > > > - PCIBridge *s = container_of(d, PCIBridge, dev); > > > pci_bridge_update_mappings(&s->sec_bus); > > > } > > > + > > > + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > > > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && > > > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { > > > + /* 0 -> 1 */ > > > + pci_bus_reset(&s->sec_bus); > > > + } > > > } > > > > > > void pci_bridge_disable_base_limit(PCIDevice *dev) > > > > Presumably this bit will have to be made writeable? > > Yes, it's already writable. > static void pci_init_wmask_bridge(PCIDevice *d) > ... > pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); Ouch, that's wrong, isn't it? Bits 15:12 are reserved, readonly, 0. I think we need the following (untested). Comments? pci: fix bridge control bit wmask Bits 12 to 15 in bridge control register are reserver and must be read-only zero, curent mask is 0xffff which makes them writeable. Fix this up by using symbolic bit names for writeable bits instead of a hardcoded constant. Signed-off-by: Michael S. Tsirkin diff --git a/hw/pci.c b/hw/pci.c index 00ec8ea..7d6d5ad 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -588,7 +588,17 @@ static void pci_init_wmask_bridge(PCIDevice *d) /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); - pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); +/* TODO: add this define to pci_regs.h in linux and then in qemu. */ +#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ + pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, + PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | + PCI_BRIDGE_CTL_ISA | + PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_VGA_16BIT | + PCI_BRIDGE_CTL_MASTER_ABORT | + PCI_BRIDGE_CTL_BUS_RESET | + PCI_BRIDGE_CTL_FAST_BACK); } static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)