| Message ID | 20170123142206.5390-1-jlu@pengutronix.de |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
On Mon, Jan 23, 2017 at 03:22:06PM +0100, Jan Luebbe wrote: > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode > called DRSGMII. > > This patch adds a corresponding phy-mode string 'drsgmii' and parses it > from DT. The MVNETA then configures the SERDES protocol value > accordingly. Hi Jan So this sets the PHY to 2.5Gbps. What about the MAC? Currently, mvneta_adjust_link() knows about SPEED_1000 and SPEED_100. Does it now need to know about SPEED_2500? mvneta_ethtool_set_link_ksettings()? Thanks Andrew
Hi Andrew, On Mo, 2017-01-23 at 19:18 +0100, Andrew Lunn wrote: > On Mon, Jan 23, 2017 at 03:22:06PM +0100, Jan Luebbe wrote: > > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode > > called DRSGMII. > > > > This patch adds a corresponding phy-mode string 'drsgmii' and parses it > > from DT. The MVNETA then configures the SERDES protocol value > > accordingly. > > So this sets the PHY to 2.5Gbps. What about the MAC? Currently, > mvneta_adjust_link() knows about SPEED_1000 and SPEED_100. Does it now > need to know about SPEED_2500? mvneta_ethtool_set_link_ksettings()? It works without any other changes. ;) Initially I looked at adding a SPEED_2500, but I wasn't sure which code would need to handle the new value. Would the path from the ethtool ioctl to the driver be enough (mvneta_ethtool_set_link_ksettings() as you said)? Regards, Jan
> It works without any other changes. ;) > > Initially I looked at adding a SPEED_2500, but I wasn't sure which code > would need to handle the new value. Would the path from the ethtool > ioctl to the driver be enough (mvneta_ethtool_set_link_ksettings() as > you said)? You have this connected to an FPGA? Do you have a traditional PHY in the FPGA? Or are you implementing something more like an Ethernet switch? I don't know this driver too well, but what often happens is the PHY performs autoneg and the phylib then calls the adjust_link function to set the MAC to what has been negotiated. So if you have a PHY attached which can do 2.5Ghz, you might be seeing calls to adjust_link with SPEED_2500. What does ethtool <devname> show? Thanks Andrew
From: Jan Luebbe <jlu@pengutronix.de> Date: Mon, 23 Jan 2017 15:22:06 +0100 > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode > called DRSGMII. > > This patch adds a corresponding phy-mode string 'drsgmii' and parses it > from DT. The MVNETA then configures the SERDES protocol value > accordingly. > > It was successfully tested on a MV78460 connected to a FPGA. > > Signed-off-by: Jan Luebbe <jlu@pengutronix.de> I still haven't seen a sufficient explanation as to why this change works without any explicit MAC programming changes to this driver. That really needs to be explained before I will apply this patch. Thanks.
On Mi, 2017-01-25 at 12:38 -0500, David Miller wrote: > I still haven't seen a sufficient explanation as to why this change > works without any explicit MAC programming changes to this driver. > > That really needs to be explained before I will apply this patch. I'll need to recheck this with the documentation and will also check what/if changes need to be done for ethtool and adjust_link as Andrew Lunn mentioned. So in any case there will be a v2 as soon as I figure out those details. Thanks, Jan
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt index 05150957ecfd..de40c5977d8f 100644 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ b/Documentation/devicetree/bindings/net/ethernet.txt @@ -29,6 +29,7 @@ The following properties are common to the Ethernet controllers: * "smii" * "xgmii" * "trgmii" + * "drsgmii" - phy-connection-type: the same as "phy-mode" property but described in ePAPR; - phy-handle: phandle, specifies a reference to a node representing a PHY device; this property is described in ePAPR and so preferred; diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index e05e22705cf7..8cb43e0d9d0e 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -105,6 +105,7 @@ #define MVNETA_SERDES_CFG 0x24A0 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 +#define MVNETA_DRSGMII_SERDES_PROTO 0x1107 #define MVNETA_TYPE_PRIO 0x24bc #define MVNETA_FORCE_UNI BIT(21) #define MVNETA_TXQ_CMD_1 0x24e4 @@ -4047,6 +4048,10 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) * SGMII or QSGMII mode, the RGMII bit needs to be set. */ switch(phy_mode) { + case PHY_INTERFACE_MODE_DRSGMII: + mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_DRSGMII_SERDES_PROTO); + ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; + break; case PHY_INTERFACE_MODE_QSGMII: mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; diff --git a/include/linux/phy.h b/include/linux/phy.h index f7d95f644eed..a3d83bc96035 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -82,6 +82,7 @@ typedef enum { PHY_INTERFACE_MODE_MOCA, PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TRGMII, + PHY_INTERFACE_MODE_DRSGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -142,6 +143,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "qsgmii"; case PHY_INTERFACE_MODE_TRGMII: return "trgmii"; + case PHY_INTERFACE_MODE_DRSGMII: + return "drsgmii"; default: return "unknown"; }
The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode called DRSGMII. This patch adds a corresponding phy-mode string 'drsgmii' and parses it from DT. The MVNETA then configures the SERDES protocol value accordingly. It was successfully tested on a MV78460 connected to a FPGA. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- Documentation/devicetree/bindings/net/ethernet.txt | 1 + drivers/net/ethernet/marvell/mvneta.c | 5 +++++ include/linux/phy.h | 3 +++ 3 files changed, 9 insertions(+)