From patchwork Tue Feb 23 22:22:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 71728 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id E4EBCE8CCE0 for ; Tue, 23 Feb 2010 23:25:04 +0100 (CET) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id AE66FC8C5CB5 for ; Tue, 23 Feb 2010 23:25:04 +0100 (CET) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.9) for (single-drop); Tue, 23 Feb 2010 23:25:04 +0100 (CET) Received: from murder (svr19.m-online.net [192.168.3.147]) by backend2 (Cyrus v2.2.12) with LMTPA; Tue, 23 Feb 2010 23:23:31 +0100 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend3.pop.m-online.net (Cyrus v2.2.13) with LMTPA; Tue, 23 Feb 2010 23:23:31 +0100 Received: from scanner-4.m-online.net (scanner-4.m-online.net [192.168.1.18]) by mail.m-online.net (Postfix) with ESMTP id 159EF200168; Tue, 23 Feb 2010 23:23:31 +0100 (CET) Received: from mxin-1.m-online.net ([192.168.6.164]) by scanner-4.m-online.net (scanner-4.m-online.net [192.168.1.18]) (amavisd-new, port 10026) with ESMTP id 01061-04; Tue, 23 Feb 2010 23:23:29 +0100 (CET) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-1.m-online.net (Postfix) with ESMTP id 3FF0C46C0A5; Tue, 23 Feb 2010 23:23:29 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5A780280A2; Tue, 23 Feb 2010 23:23:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tFo7UdE8xeWy; Tue, 23 Feb 2010 23:23:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76BBF2808A; Tue, 23 Feb 2010 23:23:19 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1685F28084 for ; Tue, 23 Feb 2010 23:23:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4pJ+vyTAG9dj for ; Tue, 23 Feb 2010 23:23:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by theia.denx.de (Postfix) with ESMTP id 1059428082 for ; Tue, 23 Feb 2010 23:23:11 +0100 (CET) Received: from d4rwin.no-ip.org (47.Red-88-19-186.staticIP.rima-tde.net [88.19.186.47]) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id 60049225173; Tue, 23 Feb 2010 23:23:11 +0100 (CET) Received: by d4rwin.no-ip.org (Postfix, from userid 1000) id D978B6B6EF; Tue, 23 Feb 2010 23:22:38 +0100 (CET) Date: Tue, 23 Feb 2010 23:22:38 +0100 From: Matthias Kaehlcke To: Tom Message-ID: <20100223222238.GM20201@darwin> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] edb93xx: Fix SDRAM initialization X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net edb93xx: Fix SDRAM initialization by issuing a precharge all command before forcing the precharge and select mode register update mode before programming the mode registers. Write to the SDRAM banks in order to force a precharge, reading causes the edb93xx boards to hang Signed-off-by: Matthias Kaehlcke --- board/edb93xx/sdram_cfg.c | 40 ++++++++++++++++++++++++++++++++-------- 1 files changed, 32 insertions(+), 8 deletions(-) diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c index 6155f0e..5070744 100644 --- a/board/edb93xx/sdram_cfg.c +++ b/board/edb93xx/sdram_cfg.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2009 Matthias Kaehlcke + * Copyright (C) 2010, 2009 + * Matthias Kaehlcke * * Copyright (C) 2006 Dominic Rath * @@ -30,9 +31,9 @@ (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) #define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 -static void force_precharge(void); +static void precharge_all_banks(void); static void setup_refresh_timer(void); static void program_mode_registers(void); @@ -47,7 +48,7 @@ void sdram_cfg(void) early_udelay(200); - force_precharge(); + precharge_all_banks(); setup_refresh_timer(); @@ -57,19 +58,37 @@ void sdram_cfg(void) writel(GLCONFIG_CKE, &sdram->glconfig); } -static void force_precharge(void) +static void precharge_all_banks(void) { + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Issue PRECHARGE ALL commands */ + writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); + /* - * Errata most EP93xx revisions say that PRECHARGE ALL isn't always - * issued. + * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always + * issued * - * Do a read from each bank to make sure they're precharged + * Cirrus proposes a workaround which consists in performing a read from + * each bank to force the precharge. This causes some boards to hang. + * Writing to the SDRAM banks instead of reading has the same + * side-effect (the SDRAM controller issues the necessary precharges), + * but is known to work on all supported boards */ PRECHARGE_BANK(0); + +#if (CONFIG_NR_DRAM_BANKS >= 2) PRECHARGE_BANK(1); +#endif + +#if (CONFIG_NR_DRAM_BANKS >= 3) PRECHARGE_BANK(2); +#endif + +#if (CONFIG_NR_DRAM_BANKS == 4) PRECHARGE_BANK(3); +#endif } static void setup_refresh_timer(void) @@ -101,6 +120,11 @@ static void setup_refresh_timer(void) static void program_mode_registers(void) { + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Select mode register update mode */ + writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); + /* * The mode registers are programmed by performing a read from each * SDRAM bank. The value of the address that is read defines the value