From patchwork Tue Jan 26 16:16:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Rubini X-Patchwork-Id: 71717 Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id 0F26A3F6C0 for ; Tue, 26 Jan 2010 17:18:08 +0100 (CET) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id 00826C960250 for ; Tue, 26 Jan 2010 17:18:08 +0100 (CET) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.9) for (single-drop); Tue, 26 Jan 2010 17:18:08 +0100 (CET) Received: from murder (svr19.m-online.net [192.168.3.147]) by backend2 (Cyrus v2.2.12) with LMTPA; Tue, 26 Jan 2010 17:17:14 +0100 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend3.pop.m-online.net (Cyrus v2.2.13) with LMTPA; Tue, 26 Jan 2010 17:17:13 +0100 Received: from scanner-3.m-online.net (scanner-3.m-online.net [192.168.1.20]) by mail.m-online.net (Postfix) with ESMTP id 40CBB200102; Tue, 26 Jan 2010 17:17:13 +0100 (CET) Received: from mxin-3.m-online.net ([192.168.6.165]) by scanner-3.m-online.net (scanner-3.m-online.net [192.168.1.20]) (amavisd-new, port 10026) with ESMTP id 05181-03; Tue, 26 Jan 2010 17:17:11 +0100 (CET) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-3.m-online.net (Postfix) with ESMTP id 3262F47A4F8; Tue, 26 Jan 2010 17:17:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4C065280AD; Tue, 26 Jan 2010 17:16:54 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 92eGd7BV59QZ; Tue, 26 Jan 2010 17:16:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 479B4280AF; Tue, 26 Jan 2010 17:16:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C4599280A4 for ; Tue, 26 Jan 2010 17:16:45 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I+rSN8GG2Uvb for ; Tue, 26 Jan 2010 17:16:45 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.gnudd.com (mail2.gnudd.com [213.203.150.91]) by theia.denx.de (Postfix) with ESMTPS id EECD828096 for ; Tue, 26 Jan 2010 17:16:30 +0100 (CET) Received: from mail.gnudd.com (localhost [127.0.0.1]) by mail.gnudd.com (8.14.3/8.14.3/Debian-5) with ESMTP id o0QGGTfE020992 for ; Tue, 26 Jan 2010 17:16:29 +0100 Received: (from rubini@localhost) by mail.gnudd.com (8.14.3/8.14.3/Submit) id o0QGGTok020991 for u-boot@lists.denx.de; Tue, 26 Jan 2010 17:16:29 +0100 Date: Tue, 26 Jan 2010 17:16:29 +0100 From: Alessandro Rubini To: u-boot@lists.denx.de Message-ID: <20100126161629.GA20986@morgana.gnudd.com> MIME-Version: 1.0 Content-Disposition: inline X-Face: #Q; A)@_4.#>0+_%y]7aBr:c"ndLp&#+2?]J; lkse\^)FP^Lr5@O0{)J; 'nny4%74.fM'n)M >ISCj.KmsL/HTxz!:Ju'pnj'Gz&. Organization: GnuDD, Device Drivers, Embedded Systems, Courses Subject: [U-Boot] [PATCH RFC 2/2] arm cp15: setup mmu and enable dcache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net This has been tested on at91sam9263 and STN8815. Again, I didn't check if it has bad effects on non-arm926 cores. Initially I had a "done" bit to only set up page tables at the beginning. However, since the aligmnent requirement was for the whole object file, this extra integer tool 16kB in BSS, so I chose to remove it. Also, note not all boards use PHYS_SDRAM, but it looks like it's the most used name (more than CONFIG_SYS_DRAM_BASE for example). Signed-off-by: Alessandro Rubini --- lib_arm/cache-cp15.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/lib_arm/cache-cp15.c b/lib_arm/cache-cp15.c index 62ed54f..257aea1 100644 --- a/lib_arm/cache-cp15.c +++ b/lib_arm/cache-cp15.c @@ -32,6 +32,35 @@ static void cp_delay (void) /* copro seems to need some delay between reading and writing */ for (i = 0; i < 100; i++) nop(); + asm volatile("" : : : "memory"); +} + +/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */ +static inline void mmu_setup(void) +{ + static u32 __attribute__((aligned(16384))) page_table[4096]; + int i; + u32 reg; + + /* Set up an identity-mapping for all 4GB, rw for everyone */ + for (i = 0; i < 4096; i++) + page_table[i] = i << 20 | (3 << 10) | 0x12; + /* Then, enable cacheable and bufferable for RAM only */ + for (i = PHYS_SDRAM >> 20; + i < ( PHYS_SDRAM + PHYS_SDRAM_SIZE) >> 20; + i++) { + page_table[i] = i << 20 | (3 << 10) | 0x1e; + } + /* Copy the page table address to cp15 */ + asm volatile("mcr p15, 0, %0, c2, c0, 0" + : : "r" (page_table) : "memory"); + /* Set the access control to all-supervisor */ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + : : "r" (~0)); + /* and enable the mmu */ + reg = get_cr(); /* get control reg. */ + cp_delay(); + set_cr(reg | CR_M); } /* cache_bit must be either CR_I or CR_C */ @@ -39,6 +68,9 @@ static void cache_enable(uint32_t cache_bit) { uint32_t reg; + /* The data cache is not active unless the mmu is enabled too */ + if (cache_bit == CR_C) + mmu_setup(); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -49,6 +81,11 @@ static void cache_disable(uint32_t cache_bit) { uint32_t reg; + if (cache_bit == CR_C) { + /* if disabling data cache, disable mmu too */ + cache_bit |= CR_M; + flush_cache(0, ~0); + } reg = get_cr(); cp_delay(); set_cr(reg & ~cache_bit);