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[88.72.191.254] by 217.119.54.77 with AES256-SHA encrypted SMTP; 16 Jan 2010 20:25:25 -0000 Message-ID: <4B5221A9.50009@scharsoft.de> Date: Sat, 16 Jan 2010 21:29:29 +0100 From: Jens Scharsig User-Agent: Thunderbird 2.0.0.23 (X11/20090817) MIME-Version: 1.0 To: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 5/8 V2 Part 3/3] add at91 SoC access with c structures X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net * insert AT91 SoC access using c-stuctures Signed-off-by: Jens Scharsig diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h index 0feed9c..78c0b16 100644 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -51,6 +51,19 @@ #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ +#define AT91_EMAC_BASE 0xfffbc000 +#define AT91_SMC_BASE 0xffffe800 +#define AT91_MATRIX_BASE 0xffffea00 + +#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 + +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY + /* * User Peripheral physical base addresses. */ @@ -114,6 +127,8 @@ #define AT91_USART2 AT91SAM9G45_BASE_US2 #define AT91_USART3 AT91SAM9G45_BASE_US3 +#endif + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 4dd8037..af0e434 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -44,6 +44,18 @@ #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 + +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 + +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 + +#ifdef CONFIG_AT91_LEGACY /* * User Peripheral physical base addresses. @@ -68,7 +80,6 @@ #define AT91SAM9RL_BASE_AC97C 0xfffd8000 #define AT91_BASE_SYS 0xffffc000 - /* * System Peripherals (offset from AT91_BASE_SYS) */ @@ -99,6 +110,7 @@ #define AT91_USART2 AT91SAM9RL_BASE_US2 #define AT91_USART3 AT91SAM9RL_BASE_US3 +#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h index e2d375b..2afac03 100644 --- a/include/asm-arm/arch-at91/gpio.h +++ b/include/asm-arm/arch-at91/gpio.h @@ -13,11 +13,14 @@ #ifndef __ASM_ARCH_AT91_GPIO_H #define __ASM_ARCH_AT91_GPIO_H + #include #include #include #include +#ifdef CONFIG_AT91_LEGACY + #define PIN_BASE 32 #define MAX_GPIO_BANKS 5 @@ -189,6 +192,7 @@ #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) + static unsigned long at91_pios[] = { AT91_PIOA, AT91_PIOB, @@ -214,154 +218,10 @@ static inline unsigned pin_to_mask(unsigned pin) return 1 << (pin % 32); } -/* - * mux the pin to the "GPIO" peripheral role. - */ -static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_PER); - return 0; -} - -/* - * mux the pin to the "A" internal peripheral role. - */ -static inline int at91_set_A_periph(unsigned pin, int use_pullup) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ASR); - __raw_writel(mask, pio + PIO_PDR); - return 0; -} - -/* - * mux the pin to the "B" internal peripheral role. - */ -static inline int at91_set_B_periph(unsigned pin, int use_pullup) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_BSR); - __raw_writel(mask, pio + PIO_PDR); - return 0; -} - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and - * configure it for an input. - */ -static inline int at91_set_gpio_input(unsigned pin, int use_pullup) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ODR); - __raw_writel(mask, pio + PIO_PER); - return 0; -} - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), - * and configure it for an output. - */ -static inline int at91_set_gpio_output(unsigned pin, int value) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + PIO_PUDR); - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); - __raw_writel(mask, pio + PIO_OER); - __raw_writel(mask, pio + PIO_PER); - return 0; -} - -/* - * enable/disable the glitch filter; mostly used with IRQ handling. - */ -static inline int at91_set_deglitch(unsigned pin, int is_on) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); - return 0; -} - -/* - * enable/disable the multi-driver; This is only valid for output and - * allows the output pin to run as an open collector output. - */ -static inline int at91_set_multi_drive(unsigned pin, int is_on) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); - return 0; -} - -static inline int gpio_direction_input(unsigned pin) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!(__raw_readl(pio + PIO_PSR) & mask)) - return -EINVAL; - __raw_writel(mask, pio + PIO_ODR); - return 0; -} - -static inline int gpio_direction_output(unsigned pin, int value) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!(__raw_readl(pio + PIO_PSR) & mask)) - return -EINVAL; - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); - __raw_writel(mask, pio + PIO_OER); - return 0; -} - -/* - * assuming the pin is muxed as a gpio output, set its value. - */ -static inline int at91_set_gpio_value(unsigned pin, int value) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); - return 0; -} - -/* - * read the pin's value (works even if it's not muxed as a gpio). - */ -static inline int at91_get_gpio_value(unsigned pin) -{ - void *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - u32 pdsr; +#define at91_set_GPIO_periph at91_set_gpio_periph +#define at91_set_A_periph at91_set_a_periph +#define at91_set_B_periph at91_set_b_periph - pdsr = __raw_readl(pio + PIO_PDSR); - return (pdsr & mask) != 0; -} #endif +#endif diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index de06a10..4ddb315 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -17,7 +17,7 @@ #include #if defined(CONFIG_AT91RM9200) -#include +#include #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #include #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index f09b2df..38d185e 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -23,6 +23,8 @@ #include +#ifdef CONFIG_AT91_LEGACY + static inline unsigned int at91_sys_read(unsigned int reg_offset) { void *addr = (void *)AT91_BASE_SYS; @@ -36,5 +38,6 @@ static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) __raw_writel(value, addr + reg_offset); } +#endif #endif diff --git a/include/i2c.h b/include/i2c.h index b754769..31088b6 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -74,6 +74,11 @@ # define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); # elif defined(CONFIG_8xx) # define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + +# elif (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; # else # define I2C_SOFT_DECLARATIONS # endif diff --git a/include/netdev.h b/include/netdev.h index a91368e..f0f86dc 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -42,6 +42,7 @@ int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ int au1x00_enet_initialize(bd_t*); +int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis);