From patchwork Tue Sep 8 20:39:34 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Albin Tonnerre X-Patchwork-Id: 71675 X-Patchwork-Delegate: info@emk-elektronik.de Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id 68569832E8DE for ; Tue, 8 Sep 2009 22:40:04 +0200 (CEST) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id 48FECC913100 for ; Tue, 8 Sep 2009 22:40:04 +0200 (CEST) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.8) for (single-drop); Tue, 08 Sep 2009 22:40:04 +0200 (CEST) Received: from murder (svr19.m-online.net [192.168.3.147]) by backend2 (Cyrus v2.2.12) with LMTPA; Tue, 08 Sep 2009 22:44:09 +0200 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend3.pop.m-online.net (Cyrus v2.2.13) with LMTPA; Tue, 08 Sep 2009 22:39:46 +0200 Received: from scanner-2.m-online.net (unknown [192.168.8.166]) by mail.m-online.net (Postfix) with ESMTP id F0BEB200088; Tue, 8 Sep 2009 22:39:45 +0200 (CEST) Received: from mxin-1.m-online.net ([192.168.2.222]) by scanner-2.m-online.net (scanner-2.m-online.net [192.168.8.166]) (amavisd-new, port 10026) with ESMTP id 19342-07-4; Tue, 8 Sep 2009 22:40:52 +0200 (CEST) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-1.m-online.net (Postfix) with ESMTP id 8E1CA46C0AA; Tue, 8 Sep 2009 22:39:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1A0FB281B9; Tue, 8 Sep 2009 22:39:40 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QXce+uF-XFkC; Tue, 8 Sep 2009 22:39:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7C925281A3; Tue, 8 Sep 2009 22:39:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34E7B2818B for ; Tue, 8 Sep 2009 22:39:26 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DwUvVx4Sdaq4 for ; Tue, 8 Sep 2009 22:39:24 +0200 (CEST) Received: from mail.free-electrons.com (mail.free-electrons.com [88.191.76.200]) by theia.denx.de (Postfix) with ESMTP id 070EB28175 for ; Tue, 8 Sep 2009 22:39:22 +0200 (CEST) Received: by mail.free-electrons.com (Postfix, from userid 106) id CC62BE16B; Tue, 8 Sep 2009 22:37:38 +0200 (CEST) Received: from localhost (lns-bzn-59-82-252-132-253.adsl.proxad.net [82.252.132.253]) by mail.free-electrons.com (Postfix) with ESMTPSA id 4B283E208; Tue, 8 Sep 2009 22:37:29 +0200 (CEST) From: Albin Tonnerre To: plagnioj@jcrosoft.com Date: Tue, 8 Sep 2009 22:39:34 +0200 Message-Id: <1252442374-25386-1-git-send-email-albin.tonnerre@free-electrons.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1252153380-28664-1-git-send-email-albin.tonnerre@free-electrons.com> References: <1252153380-28664-1-git-send-email-albin.tonnerre@free-electrons.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3] AT91: Add SD/MMC controller support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net This patch allows to use the atmel_mci SD/MMC driver on the at91 architecture. It contains: - initialization code for the MCI controller for all the supported AT91. It allows the use of only one controller even if a SoC has two controllers (anyway there's no support for it in atmel_mci as of now) - the necessary get_mci_clk_rate function - definition of MMCI_BASE for use in atmel_mci - the cpu_mmc_init function. As of now this is not used, but will be required when atmel_mci is ported to the new generic mmc API. Signed-off-by: Albin Tonnerre Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Changes since v1 - Fix the MCI controller ID in the init code for CAP9, SAM9263 and SAM9G45 - Move AT91_BASE_MCI* define to soc header - define AT91_BASE_MCI{0,1} instead of AT91_BASE_MCI for boards which have 2 controllers - rework the way MMCI_BASE is defined accordingly Changes since v2 - allow using 8-bit bus width on CPUs that support it - change the arguments of atmel_mciX_hw_init to (slot, bus) so that it's more meaningful than (bitmask) cpu/arm926ejs/at91/at91cap9_devices.c | 40 +++++++++++++++ cpu/arm926ejs/at91/at91sam9260_devices.c | 37 ++++++++++++++ cpu/arm926ejs/at91/at91sam9261_devices.c | 21 ++++++++ cpu/arm926ejs/at91/at91sam9263_devices.c | 72 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 56 +++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9rl_devices.c | 25 +++++++++ include/asm-arm/arch-at91/at91_common.h | 2 + include/asm-arm/arch-at91/at91cap9.h | 2 + include/asm-arm/arch-at91/at91sam9260.h | 1 + include/asm-arm/arch-at91/at91sam9261.h | 1 + include/asm-arm/arch-at91/at91sam9263.h | 2 + include/asm-arm/arch-at91/at91sam9g45.h | 2 + include/asm-arm/arch-at91/at91sam9rl.h | 1 + include/asm-arm/arch-at91/clk.h | 5 ++ include/asm-arm/arch-at91/memory-map.h | 6 ++ 15 files changed, 273 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..de7048b 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -79,6 +79,46 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_MCI0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA2, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA0, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } +} + +void at91_mci1_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_MCI0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA16, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA17, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA18, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + at91_set_A_periph(AT91_PIN_PA21, 1); + } +} +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index f86cb99..f724f58 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -75,6 +75,43 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA8, 0); + + switch (slot) { + case 0: + /* CMD */ + at91_set_A_periph(AT91_PIN_PA7, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA6, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + break; + case 1: + /* CMD */ + at91_set_B_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PA0, 1); + if (bus_width == 4) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + break; + } +} +#endif /* ATMEL_MCI */ + #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..be76acf 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -75,6 +75,27 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_MCI); + + /* CLK */ + at91_set_B_periph(AT91_PIN_PA2, 0); + + /* CMD */ + at91_set_B_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PA0, 1); + if (bus_width == 4) { + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_B_periph(AT91_PIN_PA6, 1); + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..c06a541 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -79,6 +79,78 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA12, 0); + + switch (slot) { + case 0: + /* CMD */ + at91_set_A_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA0, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + break; + case 1: + /* CMD */ + at91_set_A_periph(AT91_PIN_PA16, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA17, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + break; + } +} + +void at91_mci1_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI1); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA6, 0); + + switch (slot) { + case 0: + /* CMD */ + at91_set_A_periph(AT91_PIN_PA7, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA8, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + break; + case 1: + /* CMD */ + at91_set_B_periph(AT91_PIN_PA21, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PA22, 1); + if (bus_width == 4) { + at91_set_B_periph(AT91_PIN_PA23, 1); + at91_set_B_periph(AT91_PIN_PA24, 1); + at91_set_B_periph(AT91_PIN_PA25, 1); + } + break; + } +} +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..91a0546 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -75,6 +75,62 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_MCI0); + + at91_set_A_periph(AT91_PIN_PA12, 0); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA0, 1); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */ + at91_set_A_periph(AT91_PIN_PA2, 1); + switch (bus_width) { + case 8: + at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + at91_set_A_periph(AT91_PIN_PA9, 1); + case 4: + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + break; + } +} + +void at91_mci1_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_MCI1); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA31, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA22, 1); + + /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */ + at91_set_A_periph(AT91_PIN_PA23, 1); + switch (bus_width) { + case 8: + at91_set_A_periph(AT91_PIN_PA27, 1); + at91_set_A_periph(AT91_PIN_PA28, 1); + at91_set_A_periph(AT91_PIN_PA29, 1); + at91_set_A_periph(AT91_PIN_PA30, 1); + case 4: + at91_set_A_periph(AT91_PIN_PA24, 1); + at91_set_A_periph(AT91_PIN_PA25, 1); + at91_set_A_periph(AT91_PIN_PA26, 1); + break; + } +} +#endif + #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..3945e13 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -75,6 +75,31 @@ void at91_serial_hw_init(void) #endif } +/* + * The AT91SAM9RL64 is said to have 2 slots, but the datasheet doesn't + * seem to mention to what pins the second slot is assigned + */ +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(int slot, int bus_width) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_MCI); + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA2, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PA0, 1); + if (bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h index 01840ee..1c96b40 100644 --- a/include/asm-arm/arch-at91/at91_common.h +++ b/include/asm-arm/arch-at91/at91_common.h @@ -32,6 +32,8 @@ void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); void at91_serial2_hw_init(void); void at91_serial3_hw_init(void); +void at91_mci0_hw_init(int slot, int bus_width); +void at91_mci1_hw_init(int slot, int bus_width); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); void at91_uhp_hw_init(void); diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index 98bfcc7..de731ac 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -112,6 +112,8 @@ #define AT91_BASE_SPI AT91CAP9_BASE_SPI0 #define AT91_ID_UHP AT91CAP9_ID_UHP #define AT91_PMC_UHP AT91CAP9_PMC_UHP +#define AT91_BASE_MCI0 AT91CAP9_BASE_MCI0 +#define AT91_BASE_MCI1 AT91CAP9_BASE_MCI1 /* * SCKCR flags diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index f2aef8a..6b26140 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -108,6 +108,7 @@ #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define AT91_BASE_MCI0 AT91SAM9260_BASE_MCI /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index 55bd49a..48fb8f4 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -91,6 +91,7 @@ #define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 #define AT91_ID_UHP AT91SAM9261_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define AT91_BASE_MCI0 AT91SAM9261_BASE_MCI /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index d862129..4f29e65 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -111,6 +111,8 @@ #define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 #define AT91_ID_UHP AT91SAM9263_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define AT91_BASE_MCI0 AT91SAM9263_BASE_MCI0 +#define AT91_BASE_MCI1 AT91SAM9263_BASE_MCI1 /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h index d02b157..f232600 100644 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -118,6 +118,8 @@ #define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0 #define AT91_ID_UHP AT91SAM9G45_ID_UHPHS #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define AT91_BASE_MCI0 AT91SAM9G45_BASE_MCI0 +#define AT91_BASE_MCI1 AT91SAM9G45_BASE_MCI1 /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 3638f92..d26a607 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -101,6 +101,7 @@ #define AT91_BASE_SPI AT91SAM9RL_BASE_SPI #define AT91_ID_UHP AT91SAM9RL_ID_UHP +#define AT91_BASE_MCI0 AT91SAM9RL_BASE_MCI /* diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index f642dd9..457e6c9 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/memory-map.h b/include/asm-arm/arch-at91/memory-map.h index f605f37..de0aba7 100644 --- a/include/asm-arm/arch-at91/memory-map.h +++ b/include/asm-arm/arch-at91/memory-map.h @@ -32,4 +32,10 @@ #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) #define SPI0_BASE AT91_BASE_SPI +#ifndef CONFIG_AT91_MCI1 +#define MMCI_BASE AT91_BASE_MCI0 +#else +#define MMCI_BASE AT91_BASE_MCI1 +#endif + #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */