Patchwork [U-Boot,2/2] stx: add support for AMC8548 board

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Submitter Alex Dubov
Date Aug. 4, 2009, 9:26 a.m.
Message ID <736867.31259.qm@web37607.mail.mud.yahoo.com>
Download mbox | patch
Permalink /patch/71668/
State Superseded
Delegated to: Kumar Gala
Headers show

Comments

Alex Dubov - Aug. 4, 2009, 9:26 a.m.
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended
for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM
slot, ethernet on front panel and backplane, RapidIO on backplane, USB
controller on local bus (not currently enabled) and no PCI of any kind.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
 Makefile                          |    3 +
 board/stx/stxamc8548/Makefile     |   51 ++++++
 board/stx/stxamc8548/config.mk    |   32 ++++
 board/stx/stxamc8548/stxamc8548.c |  168 +++++++++++++++++++
 board/stx/stxamc8548/u-boot.lds   |  143 ++++++++++++++++
 include/configs/stxamc8548.h      |  332 +++++++++++++++++++++++++++++++++++++
 6 files changed, 729 insertions(+), 0 deletions(-)
 create mode 100644 board/stx/stxamc8548/Makefile
 create mode 100644 board/stx/stxamc8548/config.mk
 create mode 100644 board/stx/stxamc8548/stxamc8548.c
 create mode 100644 board/stx/stxamc8548/u-boot.lds
 create mode 100644 include/configs/stxamc8548.h

Patch

diff --git a/Makefile b/Makefile
index a445eba..909c2ca 100644
--- a/Makefile
+++ b/Makefile
@@ -2525,6 +2525,9 @@  sbc8560_66_config:	unconfig
 socrates_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
 
+stxamc8548_config: unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxamc8548 stx
+
 stxgp3_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx
 
diff --git a/board/stx/stxamc8548/Makefile b/board/stx/stxamc8548/Makefile
new file mode 100644
index 0000000..39387d9
--- /dev/null
+++ b/board/stx/stxamc8548/Makefile
@@ -0,0 +1,51 @@ 
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/stx/stxamc8548/config.mk b/board/stx/stxamc8548/config.mk
new file mode 100644
index 0000000..923828b
--- /dev/null
+++ b/board/stx/stxamc8548/config.mk
@@ -0,0 +1,32 @@ 
+#
+# Copyright 2009 Alex Dubov <oakad@yahoo.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# STx amc8548 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfffc0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
diff --git a/board/stx/stxamc8548/stxamc8548.c b/board/stx/stxamc8548/stxamc8548.c
new file mode 100644
index 0000000..02ef97b
--- /dev/null
+++ b/board/stx/stxamc8548/stxamc8548.c
@@ -0,0 +1,168 @@ 
+/*
+ * (C) Copyright 2009 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void local_bus_init(void);
+void sdram_init(void);
+
+char*
+get_board_name(void)
+{
+	return "STx AMC8548";
+}
+
+unsigned long
+get_clock_freq()
+{
+	return 33000000;
+}
+
+unsigned int
+get_board_version(void)
+{
+	return 0x10;
+}
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	printf ("Board: %s Version 0x%02x\n",
+		get_board_name(), get_board_version ());
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t
+initdram(int board_type)
+{
+	long dram_size = 0;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	/*
+	 * Work around to stabilize DDR DLL MSYNC_IN.
+	 * Errata DDR9 seems to have been fixed.
+	 * This is now the workaround for Errata DDR11:
+	 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+	 */
+
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	out_be32(&gur->ddrdllcr, 0x81000000);
+	sync();
+	isync();
+	udelay(200);
+#endif
+
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
+	if (clkdiv == 16) {
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+	} else if (clkdiv == 8) {
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+	} else if (clkdiv == 4) {
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+	}
+
+	out_be32(&lbc->lcrr, in_be32(&lbc->lcrr) | 0x00030000);
+
+	sync();
+	isync();
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+        ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/stx/stxamc8548/u-boot.lds b/board/stx/stxamc8548/u-boot.lds
new file mode 100644
index 0000000..57c4e51
--- /dev/null
+++ b/board/stx/stxamc8548/u-boot.lds
@@ -0,0 +1,143 @@ 
+/*
+ * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) + 0x3f000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec ADDR(.text) + 0x3fffc :
+  {
+    *(.resetvec)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x40000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/include/configs/stxamc8548.h b/include/configs/stxamc8548.h
new file mode 100644
index 0000000..c01a4bb
--- /dev/null
+++ b/include/configs/stxamc8548.h
@@ -0,0 +1,332 @@ 
+/*
+ * Copyright 2009 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * STx amc8548 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      1 /* BOOKE */
+#define CONFIG_E500       1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    1 /* MPC8548 specific */
+#define CONFIG_STXAMC8548 1 /* STXAMC8548 board specific */
+
+#define CONFIG_RIO
+
+#define CONFIG_TSEC_ENET      1 /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE  1
+#define CONFIG_INTERRUPTS     1 /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW        1 /* Use common FSL init code */
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE 1 /* toggle L2 cache */
+#define CONFIG_BTB      1 /* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END   0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS    CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM                    /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL                       /* possible DLL fix needed */
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE     0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE     CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS           0x50 /* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * One banks, 16M, using the CFI driver.
+ */
+
+#define CONFIG_SYS_BOOT_BLOCK 0xff000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
+
+#define CONFIG_SYS_BR0_PRELIM 0xff001801
+#define CONFIG_SYS_BR1_PRELIM 0xf0001001
+
+#define	CONFIG_SYS_OR0_PRELIM 0xff006e65
+#define	CONFIG_SYS_OR1_PRELIM 0xff006e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS  1     /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT   135   /* sectors per device */
+#undef  CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE     TEXT_BASE /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+
+/*
+ * Local Bus
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE   0xf0000000
+#define CONFIG_SYS_LBC_CACHE_BASE    CONFIG_SYS_LBC_OPTION_BASE
+#define CONFIG_SYS_LBC_CACHE_SIZE    64
+#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
+#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
+
+#define CONFIG_SYS_INIT_RAM_LOCK     1
+#define CONFIG_SYS_INIT_RAM_ADDR     0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END      0x4000     /* End of used area in RAM */
+
+#define CONFIG_SYS_INIT_L2_ADDR      0xf8f80000 /* relocate boot L2SRAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE     128        /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET   \
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN       (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN        (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX           2
+#undef  CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C                 /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support*/
+#undef  CONFIG_SOFT_I2C                /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE    0x7F
+#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET   0x3000
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
+#define CONFIG_SYS_RIO_MEM_BUS  0xC0000000
+#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI  1
+#endif
+
+#define CONFIG_MII        1 /* MII PHY management */
+#define CONFIG_TSEC1      1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2      1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3      1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4      1
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR    0x10
+#define TSEC2_PHY_ADDR    0x11
+#define TSEC3_PHY_ADDR    0x12
+#define TSEC4_PHY_ADDR    0x1f
+
+#define TSEC1_PHYIDX      0
+#define TSEC2_PHYIDX      0
+#define TSEC3_PHYIDX      0
+#define TSEC4_PHYIDX      0
+
+#define TSEC1_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME   "eTSEC0"
+#define CONFIG_PHY_GIGE   1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + 0x38000)
+#define CONFIG_ENV_SECT_SIZE   0x4000   /* 16K(one sector) for env */
+#define CONFIG_ENV_SIZE        0x2000
+
+#define CONFIG_LOADS_ECHO             1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE  1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef  CONFIG_CMD_FPGA
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "STxAMC8548=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024                 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256                  /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BAUDRATE  115200
+
+#define CONFIG_LOADADDR  1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10      /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS          /* the boot command will set bootargs*/
+
+#endif /* __CONFIG_H */