diff mbox

V850: Convert multiply/add and multiply/sub patterns to fma

Message ID m3sjz18b3h.fsf@redhat.com
State New
Headers show

Commit Message

Nick Clifton Nov. 16, 2010, 4:52 p.m. UTC 
Hi Guys,

  I am applying the patch below to convert the multiply-and-add and the
  multiply-and-subtract patterns in the V850 backend over to using the
  new fma operator.

Cheers
  Nick

gcc/ChangeLog
diff mbox

Patch

Index: gcc/config/v850/v850.md
===================================================================
--- gcc/config/v850/v850.md	(revision 166807)
+++ gcc/config/v850/v850.md	(working copy)
@@ -2024,24 +2024,23 @@ 
    (set_attr "type" "fpu")])
 
 ;;; multiply-add
-(define_insn "maddsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-			  (match_operand:SF 2 "register_operand" "r"))
-		 (match_operand:SF 3 "register_operand" "r")))]
+(define_insn "fmasf4"
+  [(set (match_operand:SF         0 "register_operand" "=r")
+	(fma:SF (match_operand:SF 1 "register_operand" "r")
+		(match_operand:SF 2 "register_operand" "r")
+		(match_operand:SF 3 "register_operand" "r")))]
   "TARGET_V850E2V3"
   "maddf.s %2,%1,%3,%0"
   [(set_attr "length" "4")
    (set_attr "cc" "none_0hit")
    (set_attr "type" "fpu")])
 
-
 ;;; multiply-subtract
-(define_insn "msubsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-			   (match_operand:SF 2 "register_operand" "r"))
-		  (match_operand:SF 3 "register_operand" "r")))]
+(define_insn "fmssf4"
+  [(set (match_operand:SF                 0 "register_operand" "=r")
+	(fma:SF (match_operand:SF         1 "register_operand" "r")
+		(match_operand:SF         2 "register_operand" "r")
+		(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
   "TARGET_V850E2V3"
   "msubf.s %2,%1,%3,%0"
   [(set_attr "length" "4")
@@ -2049,11 +2048,11 @@ 
    (set_attr "type" "fpu")])
 
 ;;; negative-multiply-add
-(define_insn "nmaddsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-				  (match_operand:SF 2 "register_operand" "r"))
-			 (match_operand:SF 3 "register_operand" "r"))))]
+(define_insn "fnmasf4"
+  [(set (match_operand:SF                 0 "register_operand" "=r")
+	(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+		(match_operand:SF         2 "register_operand" "r")
+		(match_operand:SF         3 "register_operand" "r")))]
   "TARGET_V850E2V3"
   "nmaddf.s %2,%1,%3,%0"
   [(set_attr "length" "4")
@@ -2061,11 +2060,11 @@ 
    (set_attr "type" "fpu")])
 
 ;; negative-multiply-subtract
-(define_insn "nmsubsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-				   (match_operand:SF 2 "register_operand" "r"))
-			  (match_operand:SF 3 "register_operand" "r"))))]
+(define_insn "fnmssf4"
+  [(set (match_operand:SF                 0 "register_operand" "=r")
+	(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+		(match_operand:SF         2 "register_operand" "r")
+		(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
   "TARGET_V850E2V3"
   "nmsubf.s %2,%1,%3,%0"
   [(set_attr "length" "4")