From patchwork Tue Nov 16 08:26:05 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 71368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 37DBFB7138 for ; Tue, 16 Nov 2010 19:37:14 +1100 (EST) Received: from localhost ([127.0.0.1]:57578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PIH2M-0005vL-1C for incoming@patchwork.ozlabs.org; Tue, 16 Nov 2010 03:37:10 -0500 Received: from [140.186.70.92] (port=36503 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PIGsk-000121-FB for qemu-devel@nongnu.org; Tue, 16 Nov 2010 03:27:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PIGro-0006yv-8o for qemu-devel@nongnu.org; Tue, 16 Nov 2010 03:26:39 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:34125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PIGrn-0006xe-LD for qemu-devel@nongnu.org; Tue, 16 Nov 2010 03:26:16 -0500 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 9569927E2F; Tue, 16 Nov 2010 17:26:12 +0900 (JST) Received: (nullmailer pid 29397 invoked by uid 1000); Tue, 16 Nov 2010 08:26:12 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Tue, 16 Nov 2010 17:26:05 +0900 Message-Id: X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v9 1/8] pci: revise pci command register initialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch cleans up command register initialization with comments. It also fixes the initialization of io/memory bit of command register. Those bits for type 1 device is RW. Those bits for type 0 device is RO = 0 if it has no io/memory BAR RW if it has io/memory BAR Signed-off-by: Isaku Yamahata --- Changes v8 -> v9 - patch squash --- hw/pci.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 57 insertions(+), 1 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 962886e..2fc8ab1 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -544,8 +544,53 @@ static void pci_init_wmask(PCIDevice *dev) dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; dev->wmask[PCI_INTERRUPT_LINE] = 0xff; + + /* + * bit 0: PCI_COMMAND_IO + * type 0: if IO BAR is used, RW + * This is handled by pci_register_bar() + * type 1: RW: + * This is fixed by pci_init_wmask_bridge() + * bit 1: PCI_COMMAND_MEMORY + * type 0: if IO BAR is used, RW + * This is handled by pci_register_bar() + * type 1: RW + * This is fixed by pci_init_wmask_bridge() + * bit 2: PCI_COMMAND_MASTER + * type 0: RW if bus master + * type 1: RW + * bit 3: PCI_COMMAND_SPECIAL + * RO=0, optionally RW: Such device should set this bit itself + * bit 4: PCI_COMMAND_INVALIDATE + * RO=0, optionally RW: Such device should set this bit itself + * bit 5: PCI_COMMAND_VGA_PALETTE + * RO=0, optionally RW: Such device should set this bit itself + * bit 6: PCI_COMMAND_PARITY + * RW with exceptions: Such device should clear this bit itself + * Given that qemu doesn't emulate pci bus cycles, so that there + * is no place to generate parity error. So just making this + * register RW is okay because there is no place which refers + * this bit. + * TODO: When device assignment tried to inject PERR# into qemu, + * some extra work would be needed. + * bit 7: PCI_COMMAND_WAIT: reserved (PCI 3.0) + * RO=0 + * bit 8: PCI_COMMAND_SERR + * RW with exceptions: Such device should clear this bit itself + * Given that qemu doesn't emulate pci bus cycles, so that there + * is no place to generate system error. So just making this + * register RW is okay because there is no place which refers + * this bit. + * TODO: When device assignment tried to inject SERR# into qemu, + * some extra work would be needed. + * bit 9: PCI_COMMAND_FAST_BACK + * RO=0, optionally RW: Such device should set this bit itself + * bit 10: PCI_COMMAND_INTX_DISABLE + * RW + * bit 11-15: reserved + */ pci_set_word(dev->wmask + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_INTX_DISABLE); memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, @@ -554,6 +599,9 @@ static void pci_init_wmask(PCIDevice *dev) static void pci_init_wmask_bridge(PCIDevice *d) { + pci_word_test_and_set_mask(d->wmask + PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and PCI_SEC_LETENCY_TIMER */ memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); @@ -791,6 +839,14 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, if (region_num == PCI_ROM_SLOT) { /* ROM enable bit is writeable */ wmask |= PCI_ROM_ADDRESS_ENABLE; + } else { + if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { + pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND, + PCI_COMMAND_IO); + } else { + pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND, + PCI_COMMAND_MEMORY); + } } pci_set_long(pci_dev->config + addr, type); if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&