@@ -376,6 +376,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_PATTERN 0xf5860000
/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_OTG 24
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
@@ -20,6 +20,10 @@ __weak void clock_init_sec(void)
{
}
+__weak void clock_init_quirk(void)
+{
+}
+
__weak void gtbus_init(void)
{
}
@@ -32,6 +36,7 @@ int clock_init(void)
#endif
clock_init_uart();
clock_init_sec();
+ clock_init_quirk();
return 0;
}
@@ -58,6 +58,17 @@ void clock_init_sec(void)
#endif
}
+void clock_init_quirk(void)
+{
+ /* without this quirk, the USB PHY cannot be used in Linux */
+#ifdef CONFIG_MACH_SUN8I_V3S
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_OTG);
+#endif
+}
+
void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
USB OTG on V3s SoC seems to need the USB OTG clock gate to be passed and the reset to be deasserted before boot, otherwise it won't work in Linux. It seems very difficult to workaround this from CCU driver in the kernel, so add this quirk. Also add a generic quirk framework in sunxi's clock initialization code. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- New patch in v2. arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + arch/arm/mach-sunxi/clock.c | 5 +++++ arch/arm/mach-sunxi/clock_sun6i.c | 11 +++++++++++ 3 files changed, 17 insertions(+)