Patchwork Re: [PATCHv4 15/15] Pass boot device list to firmware.

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Submitter Gleb Natapov
Date Nov. 15, 2010, 8:42 a.m.
Message ID <20101115084242.GG7948@redhat.com>
Download mbox | patch
Permalink /patch/71201/
State New
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Comments

Gleb Natapov - Nov. 15, 2010, 8:42 a.m.
On Sun, Nov 14, 2010 at 10:50:13PM +0000, Blue Swirl wrote:
> On Sun, Nov 14, 2010 at 3:39 PM, Gleb Natapov <gleb@redhat.com> wrote:
> >
> > Signed-off-by: Gleb Natapov <gleb@redhat.com>
> > ---
> >  hw/fw_cfg.c |   14 ++++++++++++++
> >  hw/fw_cfg.h |    4 +++-
> >  sysemu.h    |    1 +
> >  vl.c        |   51 +++++++++++++++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 69 insertions(+), 1 deletions(-)
> >
> > diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
> > index 7b9434f..f6a67db 100644
> > --- a/hw/fw_cfg.c
> > +++ b/hw/fw_cfg.c
> > @@ -53,6 +53,7 @@ struct FWCfgState {
> >     FWCfgFiles *files;
> >     uint16_t cur_entry;
> >     uint32_t cur_offset;
> > +    Notifier machine_ready;
> >  };
> >
> >  static void fw_cfg_write(FWCfgState *s, uint8_t value)
> > @@ -315,6 +316,15 @@ int fw_cfg_add_file(FWCfgState *s,  const char *filename, uint8_t *data,
> >     return 1;
> >  }
> >
> > +static void fw_cfg_machine_ready(struct Notifier* n)
> > +{
> > +    uint32_t len;
> > +    char *bootindex = get_boot_devices_list(&len);
> > +
> > +    fw_cfg_add_bytes(container_of(n, FWCfgState, machine_ready),
> > +                     FW_CFG_BOOTINDEX, (uint8_t*)bootindex, len);
> > +}
> > +
> >  FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
> >                         target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
> >  {
> > @@ -343,6 +353,10 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
> >     fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
> >     fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
> >
> > +
> > +    s->machine_ready.notify = fw_cfg_machine_ready;
> > +    qemu_add_machine_init_done_notifier(&s->machine_ready);
> > +
> >     return s;
> >  }
> >
> > diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
> > index 856bf91..4d61410 100644
> > --- a/hw/fw_cfg.h
> > +++ b/hw/fw_cfg.h
> > @@ -30,7 +30,9 @@
> >
> >  #define FW_CFG_FILE_FIRST       0x20
> >  #define FW_CFG_FILE_SLOTS       0x10
> > -#define FW_CFG_MAX_ENTRY        (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
> > +#define FW_CFG_FILE_LAST_SLOT   (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
> > +#define FW_CFG_BOOTINDEX        (FW_CFG_FILE_LAST_SLOT + 1)
> > +#define FW_CFG_MAX_ENTRY        FW_CFG_BOOTINDEX
> 
> This should be
> #define FW_CFG_MAX_ENTRY        (FW_CFG_BOOTINDEX + 1)
> because the check is like this:
>     if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
>         s->cur_entry = FW_CFG_INVALID;
> 
Yeah, will fix.

> With that change, I got the bootindex passed to OpenBIOS:
> OpenBIOS for Sparc64
> Configuration device id QEMU version 1 machine id 0
> kernel cmdline
> CPUs: 1 x SUNW,UltraSPARC-IIi
> UUID: 00000000-0000-0000-0000-000000000000
> bootindex num_strings 1
> bootindex /pbm@000001fe00000000/ide@5/drive@1/disk@0
> 
> The device path does not match exactly, but it's close:
> /pci@1fe,0/pci-ata@5/ide1@600/disk@0

pbm->pci should be solvable by the patch at the end. Were in the spec
it is allowed to abbreviate 1fe00000000 as 1fe,0? Spec allows to drop
starting zeroes but TARGET_FMT_plx definition in targphys.h has 0 after
%. I can define another one without leading zeroes. Can you suggest
a name?  TARGET_FMT_lx is poisoned. As of ATA there is no open firmware
binding spec for ATA, so everyone does what he pleases. I based my
implementation on what open firmware showing when running on qemu x86.
"pci-ata" should be "ide" according to PCI binding spec :) 

--
			Gleb.
Blue Swirl - Nov. 15, 2010, 8:29 p.m.
2010/11/15 Gleb Natapov <gleb@redhat.com>:
> On Sun, Nov 14, 2010 at 10:50:13PM +0000, Blue Swirl wrote:
>> On Sun, Nov 14, 2010 at 3:39 PM, Gleb Natapov <gleb@redhat.com> wrote:
>> >
>> > Signed-off-by: Gleb Natapov <gleb@redhat.com>
>> > ---
>> >  hw/fw_cfg.c |   14 ++++++++++++++
>> >  hw/fw_cfg.h |    4 +++-
>> >  sysemu.h    |    1 +
>> >  vl.c        |   51 +++++++++++++++++++++++++++++++++++++++++++++++++++
>> >  4 files changed, 69 insertions(+), 1 deletions(-)
>> >
>> > diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
>> > index 7b9434f..f6a67db 100644
>> > --- a/hw/fw_cfg.c
>> > +++ b/hw/fw_cfg.c
>> > @@ -53,6 +53,7 @@ struct FWCfgState {
>> >     FWCfgFiles *files;
>> >     uint16_t cur_entry;
>> >     uint32_t cur_offset;
>> > +    Notifier machine_ready;
>> >  };
>> >
>> >  static void fw_cfg_write(FWCfgState *s, uint8_t value)
>> > @@ -315,6 +316,15 @@ int fw_cfg_add_file(FWCfgState *s,  const char *filename, uint8_t *data,
>> >     return 1;
>> >  }
>> >
>> > +static void fw_cfg_machine_ready(struct Notifier* n)
>> > +{
>> > +    uint32_t len;
>> > +    char *bootindex = get_boot_devices_list(&len);
>> > +
>> > +    fw_cfg_add_bytes(container_of(n, FWCfgState, machine_ready),
>> > +                     FW_CFG_BOOTINDEX, (uint8_t*)bootindex, len);
>> > +}
>> > +
>> >  FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
>> >                         target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
>> >  {
>> > @@ -343,6 +353,10 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
>> >     fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
>> >     fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
>> >
>> > +
>> > +    s->machine_ready.notify = fw_cfg_machine_ready;
>> > +    qemu_add_machine_init_done_notifier(&s->machine_ready);
>> > +
>> >     return s;
>> >  }
>> >
>> > diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
>> > index 856bf91..4d61410 100644
>> > --- a/hw/fw_cfg.h
>> > +++ b/hw/fw_cfg.h
>> > @@ -30,7 +30,9 @@
>> >
>> >  #define FW_CFG_FILE_FIRST       0x20
>> >  #define FW_CFG_FILE_SLOTS       0x10
>> > -#define FW_CFG_MAX_ENTRY        (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
>> > +#define FW_CFG_FILE_LAST_SLOT   (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
>> > +#define FW_CFG_BOOTINDEX        (FW_CFG_FILE_LAST_SLOT + 1)
>> > +#define FW_CFG_MAX_ENTRY        FW_CFG_BOOTINDEX
>>
>> This should be
>> #define FW_CFG_MAX_ENTRY        (FW_CFG_BOOTINDEX + 1)
>> because the check is like this:
>>     if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
>>         s->cur_entry = FW_CFG_INVALID;
>>
> Yeah, will fix.
>
>> With that change, I got the bootindex passed to OpenBIOS:
>> OpenBIOS for Sparc64
>> Configuration device id QEMU version 1 machine id 0
>> kernel cmdline
>> CPUs: 1 x SUNW,UltraSPARC-IIi
>> UUID: 00000000-0000-0000-0000-000000000000
>> bootindex num_strings 1
>> bootindex /pbm@000001fe00000000/ide@5/drive@1/disk@0
>>
>> The device path does not match exactly, but it's close:
>> /pci@1fe,0/pci-ata@5/ide1@600/disk@0
>
> pbm->pci should be solvable by the patch at the end. Were in the spec
> it is allowed to abbreviate 1fe00000000 as 1fe,0? Spec allows to drop
> starting zeroes but TARGET_FMT_plx definition in targphys.h has 0 after
> %. I can define another one without leading zeroes. Can you suggest
> a name?

I think OpenBIOS for Sparc64 is not correct here, so it may be a bad
reference architecture. OBP on a real Ultra-5 used a path like this:
/pci@1f,0/pci@1,1/ide@3/disk@0,0

pci@1f,0 specifies the PCI host bridge at UPA bus port ID of 0x1f.
pci@1,1 specifies a PCI-PCI bridge.

> TARGET_FMT_lx is poisoned. As of ATA there is no open firmware
> binding spec for ATA, so everyone does what he pleases. I based my
> implementation on what open firmware showing when running on qemu x86.
> "pci-ata" should be "ide" according to PCI binding spec :)

Yes, for example there is no ATA in the Ultra-5 tree but in UltraAX it exists:
/pci@1f,4000/ide@3/ata@0,0/cmdk@0,0

> diff --git a/hw/apb_pci.c b/hw/apb_pci.c
> index c619112..643aa49 100644
> --- a/hw/apb_pci.c
> +++ b/hw/apb_pci.c
> @@ -453,6 +453,7 @@ static PCIDeviceInfo pbm_pci_host_info = {
>
>  static SysBusDeviceInfo pbm_host_info = {
>     .qdev.name = "pbm",
> +    .qdev.fw_name = "pci",

Perhaps the FW path should use device class names if no name is specified.

I'll try Sparc32 to see how this fits there.
Gleb Natapov - Nov. 16, 2010, 2:11 p.m.
On Mon, Nov 15, 2010 at 08:29:24PM +0000, Blue Swirl wrote:
> 2010/11/15 Gleb Natapov <gleb@redhat.com>:
> > On Sun, Nov 14, 2010 at 10:50:13PM +0000, Blue Swirl wrote:
> >> On Sun, Nov 14, 2010 at 3:39 PM, Gleb Natapov <gleb@redhat.com> wrote:
> >> >
> >> > Signed-off-by: Gleb Natapov <gleb@redhat.com>
> >> > ---
> >> >  hw/fw_cfg.c |   14 ++++++++++++++
> >> >  hw/fw_cfg.h |    4 +++-
> >> >  sysemu.h    |    1 +
> >> >  vl.c        |   51 +++++++++++++++++++++++++++++++++++++++++++++++++++
> >> >  4 files changed, 69 insertions(+), 1 deletions(-)
> >> >
> >> > diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
> >> > index 7b9434f..f6a67db 100644
> >> > --- a/hw/fw_cfg.c
> >> > +++ b/hw/fw_cfg.c
> >> > @@ -53,6 +53,7 @@ struct FWCfgState {
> >> >     FWCfgFiles *files;
> >> >     uint16_t cur_entry;
> >> >     uint32_t cur_offset;
> >> > +    Notifier machine_ready;
> >> >  };
> >> >
> >> >  static void fw_cfg_write(FWCfgState *s, uint8_t value)
> >> > @@ -315,6 +316,15 @@ int fw_cfg_add_file(FWCfgState *s,  const char *filename, uint8_t *data,
> >> >     return 1;
> >> >  }
> >> >
> >> > +static void fw_cfg_machine_ready(struct Notifier* n)
> >> > +{
> >> > +    uint32_t len;
> >> > +    char *bootindex = get_boot_devices_list(&len);
> >> > +
> >> > +    fw_cfg_add_bytes(container_of(n, FWCfgState, machine_ready),
> >> > +                     FW_CFG_BOOTINDEX, (uint8_t*)bootindex, len);
> >> > +}
> >> > +
> >> >  FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
> >> >                         target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
> >> >  {
> >> > @@ -343,6 +353,10 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
> >> >     fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
> >> >     fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
> >> >
> >> > +
> >> > +    s->machine_ready.notify = fw_cfg_machine_ready;
> >> > +    qemu_add_machine_init_done_notifier(&s->machine_ready);
> >> > +
> >> >     return s;
> >> >  }
> >> >
> >> > diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
> >> > index 856bf91..4d61410 100644
> >> > --- a/hw/fw_cfg.h
> >> > +++ b/hw/fw_cfg.h
> >> > @@ -30,7 +30,9 @@
> >> >
> >> >  #define FW_CFG_FILE_FIRST       0x20
> >> >  #define FW_CFG_FILE_SLOTS       0x10
> >> > -#define FW_CFG_MAX_ENTRY        (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
> >> > +#define FW_CFG_FILE_LAST_SLOT   (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
> >> > +#define FW_CFG_BOOTINDEX        (FW_CFG_FILE_LAST_SLOT + 1)
> >> > +#define FW_CFG_MAX_ENTRY        FW_CFG_BOOTINDEX
> >>
> >> This should be
> >> #define FW_CFG_MAX_ENTRY        (FW_CFG_BOOTINDEX + 1)
> >> because the check is like this:
> >>     if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
> >>         s->cur_entry = FW_CFG_INVALID;
> >>
> > Yeah, will fix.
> >
> >> With that change, I got the bootindex passed to OpenBIOS:
> >> OpenBIOS for Sparc64
> >> Configuration device id QEMU version 1 machine id 0
> >> kernel cmdline
> >> CPUs: 1 x SUNW,UltraSPARC-IIi
> >> UUID: 00000000-0000-0000-0000-000000000000
> >> bootindex num_strings 1
> >> bootindex /pbm@000001fe00000000/ide@5/drive@1/disk@0
> >>
> >> The device path does not match exactly, but it's close:
> >> /pci@1fe,0/pci-ata@5/ide1@600/disk@0
> >
> > pbm->pci should be solvable by the patch at the end. Were in the spec
> > it is allowed to abbreviate 1fe00000000 as 1fe,0? Spec allows to drop
> > starting zeroes but TARGET_FMT_plx definition in targphys.h has 0 after
> > %. I can define another one without leading zeroes. Can you suggest
> > a name?
> 
> I think OpenBIOS for Sparc64 is not correct here, so it may be a bad
> reference architecture. OBP on a real Ultra-5 used a path like this:
> /pci@1f,0/pci@1,1/ide@3/disk@0,0
> 
> pci@1f,0 specifies the PCI host bridge at UPA bus port ID of 0x1f.
According to device name qemu creates pci controller is memory mapped
at address 1fe00000000 and by looking at the code I can see that this
is indeed the case. How is UPA naming works?

> pci@1,1 specifies a PCI-PCI bridge.
> 
> > TARGET_FMT_lx is poisoned. As of ATA there is no open firmware
> > binding spec for ATA, so everyone does what he pleases. I based my
> > implementation on what open firmware showing when running on qemu x86.
> > "pci-ata" should be "ide" according to PCI binding spec :)
> 
> Yes, for example there is no ATA in the Ultra-5 tree but in UltraAX it exists:
> /pci@1f,4000/ide@3/ata@0,0/cmdk@0,0
> 
> > diff --git a/hw/apb_pci.c b/hw/apb_pci.c
> > index c619112..643aa49 100644
> > --- a/hw/apb_pci.c
> > +++ b/hw/apb_pci.c
> > @@ -453,6 +453,7 @@ static PCIDeviceInfo pbm_pci_host_info = {
> >
> >  static SysBusDeviceInfo pbm_host_info = {
> >     .qdev.name = "pbm",
> > +    .qdev.fw_name = "pci",
> 
> Perhaps the FW path should use device class names if no name is specified.
What do you mean by "device class name". We can do something like this:
if (dev->child_bus.lh_first)
	return dev->child_bus.lh_first->info->name;

i.e if there is child bus use its bus name as fw name. This will make
all pci devices to have "pci" as fw name automatically. The problem is
that theoretically same device can provide different buses.

> 
> I'll try Sparc32 to see how this fits there.

--
			Gleb.
Blue Swirl - Nov. 16, 2010, 6:30 p.m.
2010/11/16 Gleb Natapov <gleb@redhat.com>:
> On Mon, Nov 15, 2010 at 08:29:24PM +0000, Blue Swirl wrote:
>> 2010/11/15 Gleb Natapov <gleb@redhat.com>:
>> > On Sun, Nov 14, 2010 at 10:50:13PM +0000, Blue Swirl wrote:
>> >> On Sun, Nov 14, 2010 at 3:39 PM, Gleb Natapov <gleb@redhat.com> wrote:
>> >> >
>> >> > Signed-off-by: Gleb Natapov <gleb@redhat.com>
>> >> > ---
>> >> >  hw/fw_cfg.c |   14 ++++++++++++++
>> >> >  hw/fw_cfg.h |    4 +++-
>> >> >  sysemu.h    |    1 +
>> >> >  vl.c        |   51 +++++++++++++++++++++++++++++++++++++++++++++++++++
>> >> >  4 files changed, 69 insertions(+), 1 deletions(-)
>> >> >
>> >> > diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
>> >> > index 7b9434f..f6a67db 100644
>> >> > --- a/hw/fw_cfg.c
>> >> > +++ b/hw/fw_cfg.c
>> >> > @@ -53,6 +53,7 @@ struct FWCfgState {
>> >> >     FWCfgFiles *files;
>> >> >     uint16_t cur_entry;
>> >> >     uint32_t cur_offset;
>> >> > +    Notifier machine_ready;
>> >> >  };
>> >> >
>> >> >  static void fw_cfg_write(FWCfgState *s, uint8_t value)
>> >> > @@ -315,6 +316,15 @@ int fw_cfg_add_file(FWCfgState *s,  const char *filename, uint8_t *data,
>> >> >     return 1;
>> >> >  }
>> >> >
>> >> > +static void fw_cfg_machine_ready(struct Notifier* n)
>> >> > +{
>> >> > +    uint32_t len;
>> >> > +    char *bootindex = get_boot_devices_list(&len);
>> >> > +
>> >> > +    fw_cfg_add_bytes(container_of(n, FWCfgState, machine_ready),
>> >> > +                     FW_CFG_BOOTINDEX, (uint8_t*)bootindex, len);
>> >> > +}
>> >> > +
>> >> >  FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
>> >> >                         target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
>> >> >  {
>> >> > @@ -343,6 +353,10 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
>> >> >     fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
>> >> >     fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
>> >> >
>> >> > +
>> >> > +    s->machine_ready.notify = fw_cfg_machine_ready;
>> >> > +    qemu_add_machine_init_done_notifier(&s->machine_ready);
>> >> > +
>> >> >     return s;
>> >> >  }
>> >> >
>> >> > diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
>> >> > index 856bf91..4d61410 100644
>> >> > --- a/hw/fw_cfg.h
>> >> > +++ b/hw/fw_cfg.h
>> >> > @@ -30,7 +30,9 @@
>> >> >
>> >> >  #define FW_CFG_FILE_FIRST       0x20
>> >> >  #define FW_CFG_FILE_SLOTS       0x10
>> >> > -#define FW_CFG_MAX_ENTRY        (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
>> >> > +#define FW_CFG_FILE_LAST_SLOT   (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
>> >> > +#define FW_CFG_BOOTINDEX        (FW_CFG_FILE_LAST_SLOT + 1)
>> >> > +#define FW_CFG_MAX_ENTRY        FW_CFG_BOOTINDEX
>> >>
>> >> This should be
>> >> #define FW_CFG_MAX_ENTRY        (FW_CFG_BOOTINDEX + 1)
>> >> because the check is like this:
>> >>     if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
>> >>         s->cur_entry = FW_CFG_INVALID;
>> >>
>> > Yeah, will fix.
>> >
>> >> With that change, I got the bootindex passed to OpenBIOS:
>> >> OpenBIOS for Sparc64
>> >> Configuration device id QEMU version 1 machine id 0
>> >> kernel cmdline
>> >> CPUs: 1 x SUNW,UltraSPARC-IIi
>> >> UUID: 00000000-0000-0000-0000-000000000000
>> >> bootindex num_strings 1
>> >> bootindex /pbm@000001fe00000000/ide@5/drive@1/disk@0
>> >>
>> >> The device path does not match exactly, but it's close:
>> >> /pci@1fe,0/pci-ata@5/ide1@600/disk@0
>> >
>> > pbm->pci should be solvable by the patch at the end. Were in the spec
>> > it is allowed to abbreviate 1fe00000000 as 1fe,0? Spec allows to drop
>> > starting zeroes but TARGET_FMT_plx definition in targphys.h has 0 after
>> > %. I can define another one without leading zeroes. Can you suggest
>> > a name?
>>
>> I think OpenBIOS for Sparc64 is not correct here, so it may be a bad
>> reference architecture. OBP on a real Ultra-5 used a path like this:
>> /pci@1f,0/pci@1,1/ide@3/disk@0,0
>>
>> pci@1f,0 specifies the PCI host bridge at UPA bus port ID of 0x1f.
> According to device name qemu creates pci controller is memory mapped
> at address 1fe00000000 and by looking at the code I can see that this
> is indeed the case. How is UPA naming works?

No idea.

>> pci@1,1 specifies a PCI-PCI bridge.
>>
>> > TARGET_FMT_lx is poisoned. As of ATA there is no open firmware
>> > binding spec for ATA, so everyone does what he pleases. I based my
>> > implementation on what open firmware showing when running on qemu x86.
>> > "pci-ata" should be "ide" according to PCI binding spec :)
>>
>> Yes, for example there is no ATA in the Ultra-5 tree but in UltraAX it exists:
>> /pci@1f,4000/ide@3/ata@0,0/cmdk@0,0
>>
>> > diff --git a/hw/apb_pci.c b/hw/apb_pci.c
>> > index c619112..643aa49 100644
>> > --- a/hw/apb_pci.c
>> > +++ b/hw/apb_pci.c
>> > @@ -453,6 +453,7 @@ static PCIDeviceInfo pbm_pci_host_info = {
>> >
>> >  static SysBusDeviceInfo pbm_host_info = {
>> >     .qdev.name = "pbm",
>> > +    .qdev.fw_name = "pci",
>>
>> Perhaps the FW path should use device class names if no name is specified.
> What do you mean by "device class name". We can do something like this:
> if (dev->child_bus.lh_first)
>        return dev->child_bus.lh_first->info->name;
>
> i.e if there is child bus use its bus name as fw name. This will make
> all pci devices to have "pci" as fw name automatically. The problem is
> that theoretically same device can provide different buses.

I meant PCI class name, like "display" for display controllers,
"network" for NICs etc.

>> I'll try Sparc32 to see how this fits there.

Except bootindex is not implemented for SCSI.
Gleb Natapov - Nov. 16, 2010, 7:02 p.m.
On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> >> Perhaps the FW path should use device class names if no name is specified.
> > What do you mean by "device class name". We can do something like this:
> > if (dev->child_bus.lh_first)
> >        return dev->child_bus.lh_first->info->name;
> >
> > i.e if there is child bus use its bus name as fw name. This will make
> > all pci devices to have "pci" as fw name automatically. The problem is
> > that theoretically same device can provide different buses.
> 
> I meant PCI class name, like "display" for display controllers,
> "network" for NICs etc.
> 
That is what my pci bus related patch is doing already.

> >> I'll try Sparc32 to see how this fits there.
> 
> Except bootindex is not implemented for SCSI.
Will look into adding it.

--
			Gleb.
Blue Swirl - Nov. 17, 2010, 9:54 p.m.
2010/11/16 Gleb Natapov <gleb@redhat.com>:
> On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
>> >> Perhaps the FW path should use device class names if no name is specified.
>> > What do you mean by "device class name". We can do something like this:
>> > if (dev->child_bus.lh_first)
>> >        return dev->child_bus.lh_first->info->name;
>> >
>> > i.e if there is child bus use its bus name as fw name. This will make
>> > all pci devices to have "pci" as fw name automatically. The problem is
>> > that theoretically same device can provide different buses.
>>
>> I meant PCI class name, like "display" for display controllers,
>> "network" for NICs etc.
>>
> That is what my pci bus related patch is doing already.
>
>> >> I'll try Sparc32 to see how this fits there.
>>
>> Except bootindex is not implemented for SCSI.
> Will look into adding it.

Thanks. The bootindex on Sparc32 looks like this:
bootindex /esp@0000000078800000/disk@1,0
/ethernet@ffffffffffffffff/ethernet-phy@0

I don't think I got Lance setup right.

OF paths for the devices would be:
/iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
/iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000

The logic for ESP is that ESP (registers at 0x78800000, slot offset
0x880000) is handled by the DMA controller (registers at 0x78400000,
slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
Lance should be handled the same way.

This hierarchy is partly known by QEMU because DMA accesses use this
flow, but not otherwise. There is no concept of SBus slots, DMA talks
to IOMMU directly. Though in this case both ESP, Lance and their DMA
controllers are on board devices in a MACIO chip. It may be possible
to add the hierarchy information at each stage.

It should also be possible for BIOS to determine the device just from
the physical address if we ignored OF compatibility.
Gleb Natapov - Nov. 18, 2010, 10:18 a.m.
On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> >> >> Perhaps the FW path should use device class names if no name is specified.
> >> > What do you mean by "device class name". We can do something like this:
> >> > if (dev->child_bus.lh_first)
> >> >        return dev->child_bus.lh_first->info->name;
> >> >
> >> > i.e if there is child bus use its bus name as fw name. This will make
> >> > all pci devices to have "pci" as fw name automatically. The problem is
> >> > that theoretically same device can provide different buses.
> >>
> >> I meant PCI class name, like "display" for display controllers,
> >> "network" for NICs etc.
> >>
> > That is what my pci bus related patch is doing already.
> >
> >> >> I'll try Sparc32 to see how this fits there.
> >>
> >> Except bootindex is not implemented for SCSI.
> > Will look into adding it.
> 
> Thanks. The bootindex on Sparc32 looks like this:
> bootindex /esp@0000000078800000/disk@1,0
> /ethernet@ffffffffffffffff/ethernet-phy@0
> 
For arches other then x86 there is a lot of work left to be done :)
For starter exotic sparc buses should get their own get_fw_dev_path()
implementation.

> I don't think I got Lance setup right.
> 
> OF paths for the devices would be:
> /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
If qdev hierarchy does not correspond to real HW there is no much we can
do expect for fixing qdev.

> 
> The logic for ESP is that ESP (registers at 0x78800000, slot offset
> 0x880000) is handled by the DMA controller (registers at 0x78400000,
> slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> Lance should be handled the same way.
> 
> This hierarchy is partly known by QEMU because DMA accesses use this
> flow, but not otherwise. There is no concept of SBus slots, DMA talks
> to IOMMU directly. Though in this case both ESP, Lance and their DMA
> controllers are on board devices in a MACIO chip. It may be possible
> to add the hierarchy information at each stage.
> 
> It should also be possible for BIOS to determine the device just from
> the physical address if we ignored OF compatibility.
It would be nice to be OF compatible at least at some level. Of course OF
spec is not strict enough to have two different implementations produce
exactly same device path that can be compared by strcpy.  Can we apply
the series now? At least for x86 it provides useful paths and work can
be continue for other arches by interested parties.

--
			Gleb.
Michael S. Tsirkin - Nov. 18, 2010, 11:38 a.m.
On Thu, Nov 18, 2010 at 12:18:27PM +0200, Gleb Natapov wrote:
> On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> > 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> > >> >> Perhaps the FW path should use device class names if no name is specified.
> > >> > What do you mean by "device class name". We can do something like this:
> > >> > if (dev->child_bus.lh_first)
> > >> >        return dev->child_bus.lh_first->info->name;
> > >> >
> > >> > i.e if there is child bus use its bus name as fw name. This will make
> > >> > all pci devices to have "pci" as fw name automatically. The problem is
> > >> > that theoretically same device can provide different buses.
> > >>
> > >> I meant PCI class name, like "display" for display controllers,
> > >> "network" for NICs etc.
> > >>
> > > That is what my pci bus related patch is doing already.
> > >
> > >> >> I'll try Sparc32 to see how this fits there.
> > >>
> > >> Except bootindex is not implemented for SCSI.
> > > Will look into adding it.
> > 
> > Thanks. The bootindex on Sparc32 looks like this:
> > bootindex /esp@0000000078800000/disk@1,0
> > /ethernet@ffffffffffffffff/ethernet-phy@0
> > 
> For arches other then x86 there is a lot of work left to be done :)
> For starter exotic sparc buses should get their own get_fw_dev_path()
> implementation.
> 
> > I don't think I got Lance setup right.
> > 
> > OF paths for the devices would be:
> > /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> > /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
> If qdev hierarchy does not correspond to real HW there is no much we can
> do expect for fixing qdev.

That's bad.  This raises a concern: if these paths expose qdev
internals, any attempt to fix this will break migration.

> > 
> > The logic for ESP is that ESP (registers at 0x78800000, slot offset
> > 0x880000) is handled by the DMA controller (registers at 0x78400000,
> > slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> > at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> > Lance should be handled the same way.
> > 
> > This hierarchy is partly known by QEMU because DMA accesses use this
> > flow, but not otherwise. There is no concept of SBus slots, DMA talks
> > to IOMMU directly. Though in this case both ESP, Lance and their DMA
> > controllers are on board devices in a MACIO chip. It may be possible
> > to add the hierarchy information at each stage.
> > 
> > It should also be possible for BIOS to determine the device just from
> > the physical address if we ignored OF compatibility.
> It would be nice to be OF compatible at least at some level. Of course OF
> spec is not strict enough to have two different implementations produce
> exactly same device path that can be compared by strcpy.  Can we apply
> the series now? At least for x86 it provides useful paths and work can
> be continue for other arches by interested parties.
> 
> --
> 			Gleb.

Something I only now realized is that we commit
to never changing the paths for any architecture
that supports migration.
Gleb Natapov - Nov. 18, 2010, 11:45 a.m.
On Thu, Nov 18, 2010 at 01:38:31PM +0200, Michael S. Tsirkin wrote:
> On Thu, Nov 18, 2010 at 12:18:27PM +0200, Gleb Natapov wrote:
> > On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> > > 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > > > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> > > >> >> Perhaps the FW path should use device class names if no name is specified.
> > > >> > What do you mean by "device class name". We can do something like this:
> > > >> > if (dev->child_bus.lh_first)
> > > >> >        return dev->child_bus.lh_first->info->name;
> > > >> >
> > > >> > i.e if there is child bus use its bus name as fw name. This will make
> > > >> > all pci devices to have "pci" as fw name automatically. The problem is
> > > >> > that theoretically same device can provide different buses.
> > > >>
> > > >> I meant PCI class name, like "display" for display controllers,
> > > >> "network" for NICs etc.
> > > >>
> > > > That is what my pci bus related patch is doing already.
> > > >
> > > >> >> I'll try Sparc32 to see how this fits there.
> > > >>
> > > >> Except bootindex is not implemented for SCSI.
> > > > Will look into adding it.
> > > 
> > > Thanks. The bootindex on Sparc32 looks like this:
> > > bootindex /esp@0000000078800000/disk@1,0
> > > /ethernet@ffffffffffffffff/ethernet-phy@0
> > > 
> > For arches other then x86 there is a lot of work left to be done :)
> > For starter exotic sparc buses should get their own get_fw_dev_path()
> > implementation.
> > 
> > > I don't think I got Lance setup right.
> > > 
> > > OF paths for the devices would be:
> > > /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> > > /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
> > If qdev hierarchy does not correspond to real HW there is no much we can
> > do expect for fixing qdev.
> 
> That's bad.  This raises a concern: if these paths expose qdev
> internals, any attempt to fix this will break migration.
> 
The path expose internal HW hierarchy. It is designed to do so. Qdev
designed to do the same: describe HW hierarchy. If qdev fails to do so it
is broken. I do not see connection to migration at all since the path is
not used in migration code.

> > > 
> > > The logic for ESP is that ESP (registers at 0x78800000, slot offset
> > > 0x880000) is handled by the DMA controller (registers at 0x78400000,
> > > slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> > > at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> > > Lance should be handled the same way.
> > > 
> > > This hierarchy is partly known by QEMU because DMA accesses use this
> > > flow, but not otherwise. There is no concept of SBus slots, DMA talks
> > > to IOMMU directly. Though in this case both ESP, Lance and their DMA
> > > controllers are on board devices in a MACIO chip. It may be possible
> > > to add the hierarchy information at each stage.
> > > 
> > > It should also be possible for BIOS to determine the device just from
> > > the physical address if we ignored OF compatibility.
> > It would be nice to be OF compatible at least at some level. Of course OF
> > spec is not strict enough to have two different implementations produce
> > exactly same device path that can be compared by strcpy.  Can we apply
> > the series now? At least for x86 it provides useful paths and work can
> > be continue for other arches by interested parties.
> > 
> > --
> > 			Gleb.
> 
> Something I only now realized is that we commit
> to never changing the paths for any architecture
> that supports migration.
> 
No connection to migration whatsoever.

--
			Gleb.
Michael S. Tsirkin - Nov. 18, 2010, 11:52 a.m.
On Thu, Nov 18, 2010 at 01:45:04PM +0200, Gleb Natapov wrote:
> On Thu, Nov 18, 2010 at 01:38:31PM +0200, Michael S. Tsirkin wrote:
> > On Thu, Nov 18, 2010 at 12:18:27PM +0200, Gleb Natapov wrote:
> > > On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> > > > 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > > > > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> > > > >> >> Perhaps the FW path should use device class names if no name is specified.
> > > > >> > What do you mean by "device class name". We can do something like this:
> > > > >> > if (dev->child_bus.lh_first)
> > > > >> >        return dev->child_bus.lh_first->info->name;
> > > > >> >
> > > > >> > i.e if there is child bus use its bus name as fw name. This will make
> > > > >> > all pci devices to have "pci" as fw name automatically. The problem is
> > > > >> > that theoretically same device can provide different buses.
> > > > >>
> > > > >> I meant PCI class name, like "display" for display controllers,
> > > > >> "network" for NICs etc.
> > > > >>
> > > > > That is what my pci bus related patch is doing already.
> > > > >
> > > > >> >> I'll try Sparc32 to see how this fits there.
> > > > >>
> > > > >> Except bootindex is not implemented for SCSI.
> > > > > Will look into adding it.
> > > > 
> > > > Thanks. The bootindex on Sparc32 looks like this:
> > > > bootindex /esp@0000000078800000/disk@1,0
> > > > /ethernet@ffffffffffffffff/ethernet-phy@0
> > > > 
> > > For arches other then x86 there is a lot of work left to be done :)
> > > For starter exotic sparc buses should get their own get_fw_dev_path()
> > > implementation.
> > > 
> > > > I don't think I got Lance setup right.
> > > > 
> > > > OF paths for the devices would be:
> > > > /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> > > > /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
> > > If qdev hierarchy does not correspond to real HW there is no much we can
> > > do expect for fixing qdev.
> > 
> > That's bad.  This raises a concern: if these paths expose qdev
> > internals, any attempt to fix this will break migration.
> > 
> The path expose internal HW hierarchy. It is designed to do so. Qdev
> designed to do the same: describe HW hierarchy. If qdev fails to do so it
> is broken.

Yes. But since you use qdev to build up the path, a broken
qdev will give you a broken path.

> I do not see connection to migration at all since the path is
> not used in migration code.

The connection is that if we pass the list with path 1 which you define
as broken to BIOS, then migrate to a machine with an updated qemu
which has a correct path, BIOS won't be able to complete the boot.
Right? Same in reverse direction.
As solution could be a fuzzy matching
of paths that wiull let us recover.

> > > > 
> > > > The logic for ESP is that ESP (registers at 0x78800000, slot offset
> > > > 0x880000) is handled by the DMA controller (registers at 0x78400000,
> > > > slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> > > > at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> > > > Lance should be handled the same way.
> > > > 
> > > > This hierarchy is partly known by QEMU because DMA accesses use this
> > > > flow, but not otherwise. There is no concept of SBus slots, DMA talks
> > > > to IOMMU directly. Though in this case both ESP, Lance and their DMA
> > > > controllers are on board devices in a MACIO chip. It may be possible
> > > > to add the hierarchy information at each stage.
> > > > 
> > > > It should also be possible for BIOS to determine the device just from
> > > > the physical address if we ignored OF compatibility.
> > > It would be nice to be OF compatible at least at some level. Of course OF
> > > spec is not strict enough to have two different implementations produce
> > > exactly same device path that can be compared by strcpy.  Can we apply
> > > the series now? At least for x86 it provides useful paths and work can
> > > be continue for other arches by interested parties.
> > > 
> > > --
> > > 			Gleb.
> > 
> > Something I only now realized is that we commit
> > to never changing the paths for any architecture
> > that supports migration.
> > 
> No connection to migration whatsoever.

It just seems silly to use different paths for the same thing.

Besides the connection above, I was hoping to use these paths
for section names in migration. If we can't guarantee they are
stable, we'll have to roll our own, and if we do this,
with stability guarantees required for migration format,
maybe use it for other things like BIOS as well?

> --
> 			Gleb.
Gleb Natapov - Nov. 18, 2010, 12:16 p.m.
On Thu, Nov 18, 2010 at 01:52:30PM +0200, Michael S. Tsirkin wrote:
> On Thu, Nov 18, 2010 at 01:45:04PM +0200, Gleb Natapov wrote:
> > On Thu, Nov 18, 2010 at 01:38:31PM +0200, Michael S. Tsirkin wrote:
> > > On Thu, Nov 18, 2010 at 12:18:27PM +0200, Gleb Natapov wrote:
> > > > On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> > > > > 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > > > > > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> > > > > >> >> Perhaps the FW path should use device class names if no name is specified.
> > > > > >> > What do you mean by "device class name". We can do something like this:
> > > > > >> > if (dev->child_bus.lh_first)
> > > > > >> >        return dev->child_bus.lh_first->info->name;
> > > > > >> >
> > > > > >> > i.e if there is child bus use its bus name as fw name. This will make
> > > > > >> > all pci devices to have "pci" as fw name automatically. The problem is
> > > > > >> > that theoretically same device can provide different buses.
> > > > > >>
> > > > > >> I meant PCI class name, like "display" for display controllers,
> > > > > >> "network" for NICs etc.
> > > > > >>
> > > > > > That is what my pci bus related patch is doing already.
> > > > > >
> > > > > >> >> I'll try Sparc32 to see how this fits there.
> > > > > >>
> > > > > >> Except bootindex is not implemented for SCSI.
> > > > > > Will look into adding it.
> > > > > 
> > > > > Thanks. The bootindex on Sparc32 looks like this:
> > > > > bootindex /esp@0000000078800000/disk@1,0
> > > > > /ethernet@ffffffffffffffff/ethernet-phy@0
> > > > > 
> > > > For arches other then x86 there is a lot of work left to be done :)
> > > > For starter exotic sparc buses should get their own get_fw_dev_path()
> > > > implementation.
> > > > 
> > > > > I don't think I got Lance setup right.
> > > > > 
> > > > > OF paths for the devices would be:
> > > > > /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> > > > > /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
> > > > If qdev hierarchy does not correspond to real HW there is no much we can
> > > > do expect for fixing qdev.
> > > 
> > > That's bad.  This raises a concern: if these paths expose qdev
> > > internals, any attempt to fix this will break migration.
> > > 
> > The path expose internal HW hierarchy. It is designed to do so. Qdev
> > designed to do the same: describe HW hierarchy. If qdev fails to do so it
> > is broken.
> 
> Yes. But since you use qdev to build up the path, a broken
> qdev will give you a broken path.
> 
Qdev bug. Fix it like any other bug. The nice is that when you compare
device path produced by qdev and real HW you can see when qdev is wrong.

> > I do not see connection to migration at all since the path is
> > not used in migration code.
> 
> The connection is that if we pass the list with path 1 which you define
> as broken to BIOS, then migrate to a machine with an updated qemu
> which has a correct path, BIOS won't be able to complete the boot.
You solve it like you solve all such issue with -M machine type.
But the problem exists only if migration happens in a short window
between start of the boot process and BIOS reading boot order string.
After reboot new qemu should have new BIOS.

> Right? Same in reverse direction.
Reverse direction is not and never was supported.

> As solution could be a fuzzy matching
> of paths that wiull let us recover.
> 
Firmware can try its best of course, but nothing is guarantied.

> > > > > 
> > > > > The logic for ESP is that ESP (registers at 0x78800000, slot offset
> > > > > 0x880000) is handled by the DMA controller (registers at 0x78400000,
> > > > > slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> > > > > at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> > > > > Lance should be handled the same way.
> > > > > 
> > > > > This hierarchy is partly known by QEMU because DMA accesses use this
> > > > > flow, but not otherwise. There is no concept of SBus slots, DMA talks
> > > > > to IOMMU directly. Though in this case both ESP, Lance and their DMA
> > > > > controllers are on board devices in a MACIO chip. It may be possible
> > > > > to add the hierarchy information at each stage.
> > > > > 
> > > > > It should also be possible for BIOS to determine the device just from
> > > > > the physical address if we ignored OF compatibility.
> > > > It would be nice to be OF compatible at least at some level. Of course OF
> > > > spec is not strict enough to have two different implementations produce
> > > > exactly same device path that can be compared by strcpy.  Can we apply
> > > > the series now? At least for x86 it provides useful paths and work can
> > > > be continue for other arches by interested parties.
> > > > 
> > > > --
> > > > 			Gleb.
> > > 
> > > Something I only now realized is that we commit
> > > to never changing the paths for any architecture
> > > that supports migration.
> > > 
> > No connection to migration whatsoever.
> 
> It just seems silly to use different paths for the same thing.
> 
> Besides the connection above, I was hoping to use these paths
> for section names in migration. If we can't guarantee they are
> stable, we'll have to roll our own, and if we do this,
> with stability guarantees required for migration format,
> maybe use it for other things like BIOS as well?
> 
It doesn't matter what do you use for migration purposes as long as it
depend on qdev hierarchy it will have problem when qdev hierarchy
changes and if it doesn't you can't produce unique names reliably.

--
			Gleb.
Michael S. Tsirkin - Nov. 18, 2010, 12:23 p.m.
On Thu, Nov 18, 2010 at 02:16:05PM +0200, Gleb Natapov wrote:
> On Thu, Nov 18, 2010 at 01:52:30PM +0200, Michael S. Tsirkin wrote:
> > On Thu, Nov 18, 2010 at 01:45:04PM +0200, Gleb Natapov wrote:
> > > On Thu, Nov 18, 2010 at 01:38:31PM +0200, Michael S. Tsirkin wrote:
> > > > On Thu, Nov 18, 2010 at 12:18:27PM +0200, Gleb Natapov wrote:
> > > > > On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> > > > > > 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > > > > > > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> > > > > > >> >> Perhaps the FW path should use device class names if no name is specified.
> > > > > > >> > What do you mean by "device class name". We can do something like this:
> > > > > > >> > if (dev->child_bus.lh_first)
> > > > > > >> >        return dev->child_bus.lh_first->info->name;
> > > > > > >> >
> > > > > > >> > i.e if there is child bus use its bus name as fw name. This will make
> > > > > > >> > all pci devices to have "pci" as fw name automatically. The problem is
> > > > > > >> > that theoretically same device can provide different buses.
> > > > > > >>
> > > > > > >> I meant PCI class name, like "display" for display controllers,
> > > > > > >> "network" for NICs etc.
> > > > > > >>
> > > > > > > That is what my pci bus related patch is doing already.
> > > > > > >
> > > > > > >> >> I'll try Sparc32 to see how this fits there.
> > > > > > >>
> > > > > > >> Except bootindex is not implemented for SCSI.
> > > > > > > Will look into adding it.
> > > > > > 
> > > > > > Thanks. The bootindex on Sparc32 looks like this:
> > > > > > bootindex /esp@0000000078800000/disk@1,0
> > > > > > /ethernet@ffffffffffffffff/ethernet-phy@0
> > > > > > 
> > > > > For arches other then x86 there is a lot of work left to be done :)
> > > > > For starter exotic sparc buses should get their own get_fw_dev_path()
> > > > > implementation.
> > > > > 
> > > > > > I don't think I got Lance setup right.
> > > > > > 
> > > > > > OF paths for the devices would be:
> > > > > > /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> > > > > > /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
> > > > > If qdev hierarchy does not correspond to real HW there is no much we can
> > > > > do expect for fixing qdev.
> > > > 
> > > > That's bad.  This raises a concern: if these paths expose qdev
> > > > internals, any attempt to fix this will break migration.
> > > > 
> > > The path expose internal HW hierarchy. It is designed to do so. Qdev
> > > designed to do the same: describe HW hierarchy. If qdev fails to do so it
> > > is broken.
> > 
> > Yes. But since you use qdev to build up the path, a broken
> > qdev will give you a broken path.
> > 
> Qdev bug. Fix it like any other bug. The nice is that when you compare
> device path produced by qdev and real HW you can see when qdev is wrong.
> 
> > > I do not see connection to migration at all since the path is
> > > not used in migration code.
> > 
> > The connection is that if we pass the list with path 1 which you define
> > as broken to BIOS, then migrate to a machine with an updated qemu
> > which has a correct path, BIOS won't be able to complete the boot.
> You solve it like you solve all such issue with -M machine type.

So that's unavoidable if we think paths are correct.
But if we know they are wrong, we are better off
correcting them first IMO.

> But the problem exists only if migration happens in a short window
> between start of the boot process and BIOS reading boot order string.
> After reboot new qemu should have new BIOS.

That makes it even more nasty, doesn't it?

> > Right? Same in reverse direction.
> Reverse direction is not and never was supported.
> 
> > As solution could be a fuzzy matching
> > of paths that wiull let us recover.
> > 
> Firmware can try its best of course, but nothing is guarantied.

No I mean qemu could do matching fuzzily.
This way if we get a path from the old BIOS we can
survive.

> > > > > > 
> > > > > > The logic for ESP is that ESP (registers at 0x78800000, slot offset
> > > > > > 0x880000) is handled by the DMA controller (registers at 0x78400000,
> > > > > > slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> > > > > > at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> > > > > > Lance should be handled the same way.
> > > > > > 
> > > > > > This hierarchy is partly known by QEMU because DMA accesses use this
> > > > > > flow, but not otherwise. There is no concept of SBus slots, DMA talks
> > > > > > to IOMMU directly. Though in this case both ESP, Lance and their DMA
> > > > > > controllers are on board devices in a MACIO chip. It may be possible
> > > > > > to add the hierarchy information at each stage.
> > > > > > 
> > > > > > It should also be possible for BIOS to determine the device just from
> > > > > > the physical address if we ignored OF compatibility.
> > > > > It would be nice to be OF compatible at least at some level. Of course OF
> > > > > spec is not strict enough to have two different implementations produce
> > > > > exactly same device path that can be compared by strcpy.  Can we apply
> > > > > the series now? At least for x86 it provides useful paths and work can
> > > > > be continue for other arches by interested parties.
> > > > > 
> > > > > --
> > > > > 			Gleb.
> > > > 
> > > > Something I only now realized is that we commit
> > > > to never changing the paths for any architecture
> > > > that supports migration.
> > > > 
> > > No connection to migration whatsoever.
> > 
> > It just seems silly to use different paths for the same thing.
> > 
> > Besides the connection above, I was hoping to use these paths
> > for section names in migration. If we can't guarantee they are
> > stable, we'll have to roll our own, and if we do this,
> > with stability guarantees required for migration format,
> > maybe use it for other things like BIOS as well?
> > 
> It doesn't matter what do you use for migration purposes as long as it
> depend on qdev hierarchy it will have problem when qdev hierarchy
> changes and if it doesn't you can't produce unique names reliably.
> 
> --
> 			Gleb.

We can, it's not like OF is the only way to enumerate.
We could have driver-specific paths for example, exactly like we
currently have.  I.e. paths don't have to be globally unique because
each driver has it's own domain.

It seems cleaner to use an existing spec but we must figure out
how it will not become a support issue.
Gleb Natapov - Nov. 18, 2010, 12:37 p.m.
On Thu, Nov 18, 2010 at 02:23:20PM +0200, Michael S. Tsirkin wrote:
> On Thu, Nov 18, 2010 at 02:16:05PM +0200, Gleb Natapov wrote:
> > On Thu, Nov 18, 2010 at 01:52:30PM +0200, Michael S. Tsirkin wrote:
> > > On Thu, Nov 18, 2010 at 01:45:04PM +0200, Gleb Natapov wrote:
> > > > On Thu, Nov 18, 2010 at 01:38:31PM +0200, Michael S. Tsirkin wrote:
> > > > > On Thu, Nov 18, 2010 at 12:18:27PM +0200, Gleb Natapov wrote:
> > > > > > On Wed, Nov 17, 2010 at 09:54:27PM +0000, Blue Swirl wrote:
> > > > > > > 2010/11/16 Gleb Natapov <gleb@redhat.com>:
> > > > > > > > On Tue, Nov 16, 2010 at 06:30:19PM +0000, Blue Swirl wrote:
> > > > > > > >> >> Perhaps the FW path should use device class names if no name is specified.
> > > > > > > >> > What do you mean by "device class name". We can do something like this:
> > > > > > > >> > if (dev->child_bus.lh_first)
> > > > > > > >> >        return dev->child_bus.lh_first->info->name;
> > > > > > > >> >
> > > > > > > >> > i.e if there is child bus use its bus name as fw name. This will make
> > > > > > > >> > all pci devices to have "pci" as fw name automatically. The problem is
> > > > > > > >> > that theoretically same device can provide different buses.
> > > > > > > >>
> > > > > > > >> I meant PCI class name, like "display" for display controllers,
> > > > > > > >> "network" for NICs etc.
> > > > > > > >>
> > > > > > > > That is what my pci bus related patch is doing already.
> > > > > > > >
> > > > > > > >> >> I'll try Sparc32 to see how this fits there.
> > > > > > > >>
> > > > > > > >> Except bootindex is not implemented for SCSI.
> > > > > > > > Will look into adding it.
> > > > > > > 
> > > > > > > Thanks. The bootindex on Sparc32 looks like this:
> > > > > > > bootindex /esp@0000000078800000/disk@1,0
> > > > > > > /ethernet@ffffffffffffffff/ethernet-phy@0
> > > > > > > 
> > > > > > For arches other then x86 there is a lot of work left to be done :)
> > > > > > For starter exotic sparc buses should get their own get_fw_dev_path()
> > > > > > implementation.
> > > > > > 
> > > > > > > I don't think I got Lance setup right.
> > > > > > > 
> > > > > > > OF paths for the devices would be:
> > > > > > > /iommu@0,10000000/sbus@0,10001000/espdma@5,8400000/esp@5,8800000/sd@1,0
> > > > > > > /iommu@0,10000000/sbus@0,10001000/ledma@5,8400010/le@5,8c00000
> > > > > > If qdev hierarchy does not correspond to real HW there is no much we can
> > > > > > do expect for fixing qdev.
> > > > > 
> > > > > That's bad.  This raises a concern: if these paths expose qdev
> > > > > internals, any attempt to fix this will break migration.
> > > > > 
> > > > The path expose internal HW hierarchy. It is designed to do so. Qdev
> > > > designed to do the same: describe HW hierarchy. If qdev fails to do so it
> > > > is broken.
> > > 
> > > Yes. But since you use qdev to build up the path, a broken
> > > qdev will give you a broken path.
> > > 
> > Qdev bug. Fix it like any other bug. The nice is that when you compare
> > device path produced by qdev and real HW you can see when qdev is wrong.
> > 
> > > > I do not see connection to migration at all since the path is
> > > > not used in migration code.
> > > 
> > > The connection is that if we pass the list with path 1 which you define
> > > as broken to BIOS, then migrate to a machine with an updated qemu
> > > which has a correct path, BIOS won't be able to complete the boot.
> > You solve it like you solve all such issue with -M machine type.
> 
> So that's unavoidable if we think paths are correct.
> But if we know they are wrong, we are better off
> correcting them first IMO.
> 
They are correct for x86. My patch set does not even tries to cover all
HW. If sparc want to use them to it better be fixed. Or if there is enough
info in the path to determine device it may choose to use it as is.

> > But the problem exists only if migration happens in a short window
> > between start of the boot process and BIOS reading boot order string.
> > After reboot new qemu should have new BIOS.
> 
> That makes it even more nasty, doesn't it?
No.

> 
> > > Right? Same in reverse direction.
> > Reverse direction is not and never was supported.
> > 
> > > As solution could be a fuzzy matching
> > > of paths that wiull let us recover.
> > > 
> > Firmware can try its best of course, but nothing is guarantied.
> 
> No I mean qemu could do matching fuzzily.
> This way if we get a path from the old BIOS we can
> survive.
Qemu does not take paths from BIOS so I don't know what are you talking
about here.

> 
> > > > > > > 
> > > > > > > The logic for ESP is that ESP (registers at 0x78800000, slot offset
> > > > > > > 0x880000) is handled by the DMA controller (registers at 0x78400000,
> > > > > > > slot offset 0x840000), they are in a SBus slot #5, and SBus (registers
> > > > > > > at 0x10001000) is in turn handled by IOMMU (registers at 0x10000000).
> > > > > > > Lance should be handled the same way.
> > > > > > > 
> > > > > > > This hierarchy is partly known by QEMU because DMA accesses use this
> > > > > > > flow, but not otherwise. There is no concept of SBus slots, DMA talks
> > > > > > > to IOMMU directly. Though in this case both ESP, Lance and their DMA
> > > > > > > controllers are on board devices in a MACIO chip. It may be possible
> > > > > > > to add the hierarchy information at each stage.
> > > > > > > 
> > > > > > > It should also be possible for BIOS to determine the device just from
> > > > > > > the physical address if we ignored OF compatibility.
> > > > > > It would be nice to be OF compatible at least at some level. Of course OF
> > > > > > spec is not strict enough to have two different implementations produce
> > > > > > exactly same device path that can be compared by strcpy.  Can we apply
> > > > > > the series now? At least for x86 it provides useful paths and work can
> > > > > > be continue for other arches by interested parties.
> > > > > > 
> > > > > > --
> > > > > > 			Gleb.
> > > > > 
> > > > > Something I only now realized is that we commit
> > > > > to never changing the paths for any architecture
> > > > > that supports migration.
> > > > > 
> > > > No connection to migration whatsoever.
> > > 
> > > It just seems silly to use different paths for the same thing.
> > > 
> > > Besides the connection above, I was hoping to use these paths
> > > for section names in migration. If we can't guarantee they are
> > > stable, we'll have to roll our own, and if we do this,
> > > with stability guarantees required for migration format,
> > > maybe use it for other things like BIOS as well?
> > > 
> > It doesn't matter what do you use for migration purposes as long as it
> > depend on qdev hierarchy it will have problem when qdev hierarchy
> > changes and if it doesn't you can't produce unique names reliably.
> > 
> > --
> > 			Gleb.
> 
> We can, it's not like OF is the only way to enumerate.
> We could have driver-specific paths for example, exactly like we
> currently have.  I.e. paths don't have to be globally unique because
> each driver has it's own domain.
> 
What we have currently is not even close to be correct. It happens to
work since it is implemented only for one bus type and we can have only
one of this bus right now. And of course it is not suitable for passing
boot path to FW since it does not describe path to device.


> It seems cleaner to use an existing spec but we must figure out
> how it will not become a support issue.
> 
If you think you can figure out how to describe device path (or even
give globally unique name to device) and to not depend on internal qdev
implementation go ahead and do that for migration.

--
			Gleb.
Michael S. Tsirkin - Nov. 18, 2010, 1:12 p.m.
On Thu, Nov 18, 2010 at 02:37:08PM +0200, Gleb Natapov wrote:
> > So that's unavoidable if we think paths are correct.
> > But if we know they are wrong, we are better off
> > correcting them first IMO.
> > 
> They are correct for x86. My patch set does not even tries to cover all
> HW. If sparc want to use them to it better be fixed. Or if there is enough
> info in the path to determine device it may choose to use it as is.

Fair enough I guess.

> > > But the problem exists only if migration happens in a short window
> > > between start of the boot process and BIOS reading boot order string.
> > > After reboot new qemu should have new BIOS.
> > 
> > That makes it even more nasty, doesn't it?
> No.

Nasty as in hard to reproduce.
Gleb Natapov - Nov. 18, 2010, 1:16 p.m.
On Thu, Nov 18, 2010 at 03:12:02PM +0200, Michael S. Tsirkin wrote:
> On Thu, Nov 18, 2010 at 02:37:08PM +0200, Gleb Natapov wrote:
> > > So that's unavoidable if we think paths are correct.
> > > But if we know they are wrong, we are better off
> > > correcting them first IMO.
> > > 
> > They are correct for x86. My patch set does not even tries to cover all
> > HW. If sparc want to use them to it better be fixed. Or if there is enough
> > info in the path to determine device it may choose to use it as is.
> 
> Fair enough I guess.
> 
> > > > But the problem exists only if migration happens in a short window
> > > > between start of the boot process and BIOS reading boot order string.
> > > > After reboot new qemu should have new BIOS.
> > > 
> > > That makes it even more nasty, doesn't it?
> > No.
> 
> Nasty as in hard to reproduce.
> 
It is very easy to reproduce if you know what you are looking for :).
Just stick sleep() in correct place in the BIOS.
 
--
			Gleb.

Patch

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index c619112..643aa49 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -453,6 +453,7 @@  static PCIDeviceInfo pbm_pci_host_info = {
 
 static SysBusDeviceInfo pbm_host_info = {
     .qdev.name = "pbm",
+    .qdev.fw_name = "pci",
     .qdev.size = sizeof(APBState),
     .qdev.reset = pci_pbm_reset,
     .init = pci_pbm_init_device,