Patchwork [v8,10/11] x3130/upstream: support aer

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Submitter Isaku Yamahata
Date Nov. 15, 2010, 7:30 a.m.
Message ID <4201ea60f5be71bb179c9e8e0e4f61bf7d39ca84.1289805831.git.yamahata@valinux.co.jp>
Download mbox | patch
Permalink /patch/71188/
State New
Headers show

Comments

Isaku Yamahata - Nov. 15, 2010, 7:30 a.m.
add aer support.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/xio3130_upstream.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

Patch

diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index d9d637f..29bc814 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -41,7 +41,7 @@  static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
     pci_bridge_write_config(d, address, val, len);
     pcie_cap_flr_write_config(d, address, val, len);
     msi_write_config(d, address, val, len);
-    /* TODO: AER */
+    pcie_aer_write_config(d, address, val, len);
 }
 
 static void xio3130_upstream_reset(DeviceState *qdev)
@@ -89,14 +89,14 @@  static int xio3130_upstream_initfn(PCIDevice *d)
     pcie_cap_flr_init(d);
 
     pcie_cap_deverr_init(d);
-    /* TODO: AER */
+    pcie_aer_init(d, XIO3130_AER_OFFSET);
 
     return 0;
 }
 
 static int xio3130_upstream_exitfn(PCIDevice *d)
 {
-    /* TODO: AER */
+    pcie_aer_exit(d);
     msi_uninit(d);
     pcie_cap_exit(d);
     return pci_bridge_exitfn(d);
@@ -131,7 +131,8 @@  static const VMStateDescription vmstate_xio3130_upstream = {
     .minimum_version_id_old = 1,
     .fields = (VMStateField[]) {
         VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
-        /* TODO: AER */
+        VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
+                       PCIEAERLog),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -151,7 +152,8 @@  static PCIDeviceInfo xio3130_upstream_info = {
 
     .qdev.props = (Property[]) {
         DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
-        /* TODO: AER */
+        DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
+                           PCIE_AER_LOG_MAX_DEFAULT),
         DEFINE_PROP_END_OF_LIST(),
     }
 };