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[U-Boot,PATCHv2,2/2] ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

Message ID 1483695671-11241-2-git-send-email-Zhiqiang.Hou@nxp.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Z.Q. Hou Jan. 6, 2017, 9:41 a.m. UTC
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - No change 

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..f71a243 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,5 +1,6 @@ 
 config ARCH_LS1012A
 	bool
+	select ARMV8_SET_SMPEN
 	select FSL_LSCH2
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
@@ -7,6 +8,7 @@  config ARCH_LS1012A
 
 config ARCH_LS1043A
 	bool
+	select ARMV8_SET_SMPEN
 	select FSL_LSCH2
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
@@ -15,6 +17,7 @@  config ARCH_LS1043A
 
 config ARCH_LS1046A
 	bool
+	select ARMV8_SET_SMPEN
 	select FSL_LSCH2
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR4
@@ -24,6 +27,7 @@  config ARCH_LS1046A
 
 config ARCH_LS2080A
 	bool
+	select ARMV8_SET_SMPEN
 	select FSL_LSCH3
 	select SYS_FSL_DDR4
 	select SYS_FSL_DDR_LE