From patchwork Fri Jan 6 09:12:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: linshunquan 00354166 X-Patchwork-Id: 711763 X-Patchwork-Delegate: cyrille.pitchen@atmel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tvzvX49syz9sQw for ; Fri, 6 Jan 2017 20:36:24 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cPQwf-0004w9-Q4; Fri, 06 Jan 2017 09:36:21 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cPQw8-0003G8-50 for linux-mtd@lists.infradead.org; Fri, 06 Jan 2017 09:36:20 +0000 Received: from 172.24.1.136 (EHLO szxeml430-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXN33255; Fri, 06 Jan 2017 17:31:02 +0800 (CST) Received: from ubuntu.huawei.com (10.67.212.210) by szxeml430-hub.china.huawei.com (10.82.67.185) with Microsoft SMTP Server id 14.3.235.1; Fri, 6 Jan 2017 17:30:48 +0800 From: linshunquan 00354166 To: , , , , , , , Subject: [PATCH v1] mtd: spi nor: modify the boot and flash type of FMC Date: Fri, 6 Jan 2017 17:12:11 +0800 Message-ID: <1483693931-22249-1-git-send-email-linshunquan1@hisilicon.com> X-Mailer: git-send-email 2.3.7 MIME-Version: 1.0 X-Originating-IP: [10.67.212.210] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.586F63D8.0255, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b9e42cca632ec8848f7de90f4e543c2e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170106_013618_518377_F50CE28A X-CRM114-Status: GOOD ( 11.01 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suwenping@hisilicon.com, devicetree@vger.kernel.org, howell.yang@hisilicon.com, jalen.hsu@hisilicon.com, linux-kernel@vger.kernel.org, raojun@hisilicon.com, kevin.lixu@hisilicon.com, linux-mtd@lists.infradead.org, linshunquan 00354166 , lvkuanliang@hisilicon.com, xuejiancheng@hisilicon.com Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org (1) The HiSilicon Flash Memory Controller(FMC) is a multi-functions device which supports SPI Nor flash controller, SPI nand Flash controller and parallel nand flash controller. So when we are prepare to operation SPI Nor, we should make sure the flash type is SPI Nor. (2) Make sure the boot type is Normal Type before initialize the SPI Nor controller. Signed-off-by: linshunquan 00354166 --- drivers/mtd/spi-nor/hisi-sfc.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c index 20378b0..7855024 100644 --- a/drivers/mtd/spi-nor/hisi-sfc.c +++ b/drivers/mtd/spi-nor/hisi-sfc.c @@ -32,6 +32,8 @@ #define FMC_CFG_OP_MODE_MASK BIT_MASK(0) #define FMC_CFG_OP_MODE_BOOT 0 #define FMC_CFG_OP_MODE_NORMAL 1 +#define FMC_CFG_OP_MODE_SEL(mode) ((mode) & 0x1) +#define FMC_CFG_FLASH_SEL_SPI_NOR (0x0 << 1) #define FMC_CFG_FLASH_SEL(type) (((type) & 0x3) << 1) #define FMC_CFG_FLASH_SEL_MASK 0x6 #define FMC_ECC_TYPE(type) (((type) & 0x7) << 5) @@ -141,10 +143,36 @@ static int get_if_type(enum read_mode flash_read) return if_type; } +static void spi_nor_switch_spi_type(struct hifmc_host *host) +{ + unsigned int reg; + + reg = readl(host->regbase + FMC_CFG); + if ((reg & FMC_CFG_FLASH_SEL_MASK) + == FMC_CFG_FLASH_SEL_SPI_NOR) + return; + + /* if the flash type isn't spi nor, change it */ + reg &= ~FMC_CFG_FLASH_SEL_MASK; + reg |= FMC_CFG_FLASH_SEL(0); + writel(reg, host->regbase + FMC_CFG); +} + static void hisi_spi_nor_init(struct hifmc_host *host) { u32 reg; + /* switch the flash type to spi nor */ + spi_nor_switch_spi_type(host); + + /* set the boot mode to normal */ + reg = readl(host->regbase + FMC_CFG); + if ((reg & FMC_CFG_OP_MODE_MASK) == FMC_CFG_OP_MODE_BOOT) { + reg |= FMC_CFG_OP_MODE_SEL(FMC_CFG_OP_MODE_NORMAL); + writel(reg, host->regbase + FMC_CFG); + } + + /* set timming */ reg = TIMING_CFG_TCSH(CS_HOLD_TIME) | TIMING_CFG_TCSS(CS_SETUP_TIME) | TIMING_CFG_TSHSL(CS_DESELECT_TIME); @@ -167,6 +195,8 @@ static int hisi_spi_nor_prep(struct spi_nor *nor, enum spi_nor_ops ops) if (ret) goto out; + spi_nor_switch_spi_type(host); + return 0; out: