diff mbox

[U-Boot,04/12] aspeed: Add sysreset driver

Message ID 20170104194656.124368-5-maxims@google.com
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Maxim Sloyko Jan. 4, 2017, 7:46 p.m. UTC 
The driver uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0)

Signed-off-by: Maxim Sloyko <maxims@google.com>
---

 drivers/sysreset/Makefile       |  1 +
 drivers/sysreset/sysreset_ast.c | 55 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_ast.c

Comments

Simon Glass Jan. 14, 2017, 5:14 p.m. UTC | #1 
On 4 January 2017 at 12:46, Maxim Sloyko <maxims@google.com> wrote:
> The driver uses watchdog timer to do resets and particular
> watchdog device to use is hardcoded (0)
>
> Signed-off-by: Maxim Sloyko <maxims@google.com>
> ---
>
>  drivers/sysreset/Makefile       |  1 +
>  drivers/sysreset/sysreset_ast.c | 55 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 56 insertions(+)
>  create mode 100644 drivers/sysreset/sysreset_ast.c

Reviewed-by: Simon Glass <sjg@chromium.org>
diff mbox

Patch

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index fa75cc52de..37638a8eea 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -14,3 +14,4 @@  obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
+obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c
new file mode 100644
index 0000000000..a0ab12851d
--- /dev/null
+++ b/drivers/sysreset/sysreset_ast.c
@@ -0,0 +1,55 @@ 
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+
+/* Number of Watchdog Timer ticks before reset */
+#define AST_WDT_RESET_TIMEOUT	10
+#define AST_WDT_FOR_RESET	0
+
+static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct ast_wdt *wdt = ast_get_wdt(AST_WDT_FOR_RESET);
+	u32 reset_mode = 0;
+
+	if (IS_ERR(wdt))
+		return PTR_ERR(wdt);
+
+	switch (type) {
+	case SYSRESET_WARM:
+		reset_mode = WDT_CTRL_RESET_CPU;
+		break;
+	case SYSRESET_COLD:
+		reset_mode = WDT_CTRL_RESET_CHIP;
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	/* Clear reset mode bits */
+	clrsetbits_le32(&wdt->ctrl,
+			(WDT_CTRL_RESET_MODE_MASK << WDT_CTRL_RESET_MODE_SHIFT),
+			(reset_mode << WDT_CTRL_RESET_MODE_SHIFT));
+	wdt_start(wdt, AST_WDT_RESET_TIMEOUT);
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops ast_sysreset = {
+	.request	= ast_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_ast) = {
+	.name	= "ast_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &ast_sysreset,
+};