Patchwork pci: split config update for dev assignment

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Submitter Michael S. Tsirkin
Date Nov. 13, 2010, 9:21 p.m.
Message ID <20101113212107.GA24071@redhat.com>
Download mbox | patch
Permalink /patch/71072/
State New
Headers show

Comments

Michael S. Tsirkin - Nov. 13, 2010, 9:21 p.m.
Device assignment in qemu-kvm wants to update
config array without any side-efects.
Make it easier to do so.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---

Alex, I think your work on dev assignment will be easier if I apply
this on qemu.kvm. Right? Let me know.

 hw/pci.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)
Alex Williamson - Nov. 15, 2010, 4:11 a.m.
On Sat, 2010-11-13 at 23:21 +0200, Michael S. Tsirkin wrote:
> Device assignment in qemu-kvm wants to update
> config array without any side-efects.
> Make it easier to do so.

This isn't exactly true.  The change is a side-effect of qemu-kvm
capability support currently being broken wrt wmask.  Device assignment
is just trying to make use of it.

> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> 
> Alex, I think your work on dev assignment will be easier if I apply
> this on qemu.kvm. Right? Let me know.

It might make merging easier, I don't really know how you handle that,
but I wonder if the right (although much more work on my part) is to
push my 8/9 patch down in my queue.  That removes
pci_default_cap_write_config, then my current 1/9 patch isn't really
needed and this merge conflict goes away.  Let me know.  Thanks,

Alex

>  hw/pci.c |   12 ++++++++++--
>  1 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/pci.c b/hw/pci.c
> index 8f6fcf8..30e1603 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -996,10 +996,10 @@ uint32_t pci_default_read_config(PCIDevice *d,
>      return le32_to_cpu(val);
>  }
>  
> -void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> +static void pci_update_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
>  {
> -    int i, was_irq_disabled = pci_irq_disabled(d);
>      uint32_t config_size = pci_config_size(d);
> +    int i;
>  
>      for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
>          uint8_t wmask = d->wmask[addr + i];
> @@ -1008,6 +1008,14 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
>          d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
>          d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
>      }
> +}
> +
> +void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
> +{
> +    int was_irq_disabled = pci_irq_disabled(d);
> +
> +    pci_update_config(d, addr, val, l);
> +
>      if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
>          ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
>          ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||

Patch

diff --git a/hw/pci.c b/hw/pci.c
index 8f6fcf8..30e1603 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -996,10 +996,10 @@  uint32_t pci_default_read_config(PCIDevice *d,
     return le32_to_cpu(val);
 }
 
-void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
+static void pci_update_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 {
-    int i, was_irq_disabled = pci_irq_disabled(d);
     uint32_t config_size = pci_config_size(d);
+    int i;
 
     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
         uint8_t wmask = d->wmask[addr + i];
@@ -1008,6 +1008,14 @@  void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
     }
+}
+
+void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
+{
+    int was_irq_disabled = pci_irq_disabled(d);
+
+    pci_update_config(d, addr, val, l);
+
     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||