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[U-Boot,v2,07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

Message ID 1482990285-3448-7-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Chee, Tien Fong Dec. 29, 2016, 5:44 a.m. UTC 
From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
---
 configs/socfpga_arria10_defconfig | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig
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Patch

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
new file mode 100644
index 0000000..422261b
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,16 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y