@@ -644,10 +644,14 @@ static void pci_init_wmask(PCIDevice *dev)
/*
* bit 0: PCI_COMMAND_IO
* type 0: if IO BAR is used, RW
- * type 1: RW
+ * This is handled by pci_register_bar()
+ * type 1: RW:
+ * This is fixed by pci_init_wmask_bridge()
* bit 1: PCI_COMMAND_MEMORY
* type 0: if IO BAR is used, RW
+ * This is handled by pci_register_bar()
* type 1: RW
+ * This is fixed by pci_init_wmask_bridge()
* bit 2: PCI_COMMAND_MASTER
* type 0: RW if bus master
* type 1: RW
@@ -682,8 +686,7 @@ static void pci_init_wmask(PCIDevice *dev)
* bit 11-15: reserved
*/
pci_set_word(dev->wmask + PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
- PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+ PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
PCI_COMMAND_INTX_DISABLE);
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
@@ -692,6 +695,9 @@ static void pci_init_wmask(PCIDevice *dev)
static void pci_init_wmask_bridge(PCIDevice *d)
{
+ pci_word_test_and_set_mask(d->wmask + PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
PCI_SEC_LETENCY_TIMER */
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
@@ -929,6 +935,14 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
if (region_num == PCI_ROM_SLOT) {
/* ROM enable bit is writeable */
wmask |= PCI_ROM_ADDRESS_ENABLE;
+ } else {
+ if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
+ pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND,
+ PCI_COMMAND_IO);
+ } else {
+ pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND,
+ PCI_COMMAND_MEMORY);
+ }
}
pci_set_long(pci_dev->config + addr, type);
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
This patch fixes the initialization of io/memory bit of command register. Those bits for type 1 device is RW. Those bits for type 0 device is RO = 0 if it has no io/memory BAR RW if it has io/memory BAR Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> --- hw/pci.c | 20 +++++++++++++++++--- 1 files changed, 17 insertions(+), 3 deletions(-)