From patchwork Fri Nov 12 09:51:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 70944 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A8848B7128 for ; Fri, 12 Nov 2010 20:53:30 +1100 (EST) Received: from localhost ([127.0.0.1]:52668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGqJv-00034y-7m for incoming@patchwork.ozlabs.org; Fri, 12 Nov 2010 04:53:23 -0500 Received: from [140.186.70.92] (port=44948 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGqIN-000334-KP for qemu-devel@nongnu.org; Fri, 12 Nov 2010 04:51:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGqIL-0001I7-Hf for qemu-devel@nongnu.org; Fri, 12 Nov 2010 04:51:47 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:33352) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGqIL-0001HK-2G for qemu-devel@nongnu.org; Fri, 12 Nov 2010 04:51:45 -0500 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 9749B87492; Fri, 12 Nov 2010 18:51:42 +0900 (JST) Received: (nullmailer pid 26943 invoked by uid 1000); Fri, 12 Nov 2010 09:51:42 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Fri, 12 Nov 2010 18:51:42 +0900 Message-Id: <688ed07d5170f8ec5c7df190622048664f1036eb.1289555375.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp, mst@redhat.com Subject: [Qemu-devel] [PATCH 4/4] pci: clean up of pci status register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch refine the initialization/reset of pci status registers. Signed-off-by: Isaku Yamahata --- hw/pci.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 files changed, 38 insertions(+), 2 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index a16e763..184db6c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -154,6 +154,9 @@ static void pci_device_reset(PCIDevice *dev) pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, pci_get_word(dev->wmask + PCI_COMMAND) | pci_get_word(dev->w1cmask + PCI_COMMAND)); + pci_word_test_and_clear_mask(dev->config + PCI_STATUS, + pci_get_word(dev->wmask + PCI_STATUS) | + pci_get_word(dev->w1cmask + PCI_STATUS)); dev->config[PCI_CACHE_LINE_SIZE] = 0x0; dev->config[PCI_INTERRUPT_LINE] = 0x0; for (r = 0; r < PCI_NUM_REGIONS; ++r) { @@ -636,7 +639,7 @@ static void pci_init_cmask(PCIDevice *dev) dev->cmask[PCI_CAPABILITY_LIST] = 0xff; } -static void pci_init_wmask(PCIDevice *dev) +static void pci_init_wmask_w1cmask(PCIDevice *dev) { int config_size = pci_config_size(dev); @@ -691,6 +694,39 @@ static void pci_init_wmask(PCIDevice *dev) PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_INTX_DISABLE); + /* + * bit 0-2: reserved + * bit 3: PCI_STATUS_INTERRUPT: RO + * bit 4: PCI_STATUS_CAP_LIST: RO + * bit 5: PCI_STATUS_66MHZ: RO + * bit 6: PCI_STATUS_UDF: reserved (PCI 2.2-) + * bit 7: PCI_STATUS_FAST_BACK: RO + * bit 8: PCI_STATUS_PARITY + * type 0: RW for bus master + * type 1: RW1C + * bit 9-10: PCI_STATUS_DEVSEL: RO + * bit 11: PCI_STATUS_SIG_TARGET_ABORT + * type 0: RW1C for targets that is capable of terminating + * a transaction. + * type 1: RW1C + * bit 12: PCI_STATUS_REC_TARGET_ABORT + * type 0: RW1C for masters + * type 1: RW1C + * bit 13: PCI_STATUS_REC_MASTER_ABORT + * type 0: RW1C for masters + * type 1: RW1C + * bit 14: PCI_STATUS_SIG_SYSTEM_ERROR + * type 0: RW1C with execptions + * type 1: RW1C + * bit : PCI_STATUS_DETECTED_PARITY: RW1C + * + * It's safe to set w1mask even for RO. + */ + pci_set_word(dev->w1cmask + PCI_STATUS, + PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | + PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | + PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); + memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, config_size - PCI_CONFIG_HEADER_SIZE); } @@ -821,7 +857,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, pci_set_default_subsystem_id(pci_dev); } pci_init_cmask(pci_dev); - pci_init_wmask(pci_dev); + pci_init_wmask_w1cmask(pci_dev); if (is_bridge) { pci_init_wmask_bridge(pci_dev); }