From patchwork Fri Nov 12 02:55:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 70919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1E12B713E for ; Fri, 12 Nov 2010 14:08:40 +1100 (EST) Received: from localhost ([127.0.0.1]:56369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGjrn-00039T-K0 for incoming@patchwork.ozlabs.org; Thu, 11 Nov 2010 21:59:55 -0500 Received: from [140.186.70.92] (port=47862 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGjnW-0000pR-QU for qemu-devel@nongnu.org; Thu, 11 Nov 2010 21:55:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGjnN-0000PS-Hx for qemu-devel@nongnu.org; Thu, 11 Nov 2010 21:55:22 -0500 Received: from mx1.redhat.com ([209.132.183.28]:24343) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGjnN-0000PO-3t for qemu-devel@nongnu.org; Thu, 11 Nov 2010 21:55:21 -0500 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAC2tKIK029303 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 11 Nov 2010 21:55:20 -0500 Received: from s20.home (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id oAC2tJkX009103; Thu, 11 Nov 2010 21:55:19 -0500 From: Alex Williamson To: kvm@vger.kernel.org Date: Thu, 11 Nov 2010 19:55:18 -0700 Message-ID: <20101112025507.31423.8010.stgit@s20.home> In-Reply-To: <20101112024710.31423.99667.stgit@s20.home> References: <20101112024710.31423.99667.stgit@s20.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: chrisw@redhat.com, alex.williamson@redhat.com, qemu-devel@nongnu.org, mst@redhat.com Subject: [Qemu-devel] [PATCH 2/8] pci: Remove pci_enable_capability_support() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This interface doesn't make much sense, adding a capability can take care of everything, just provide a means to register capability read/write handlers. Device assignment does it's own thing, so requires a couple ugly hacks that will be cleaned by subsequent patches. Signed-off-by: Alex Williamson --- hw/device-assignment.c | 12 ++++++++--- hw/pci.c | 52 +++++++++++++++++++++--------------------------- hw/pci.h | 9 +++----- 3 files changed, 35 insertions(+), 38 deletions(-) diff --git a/hw/device-assignment.c b/hw/device-assignment.c index bde231d..311c197 100644 --- a/hw/device-assignment.c +++ b/hw/device-assignment.c @@ -1292,7 +1292,12 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev) PCIRegion *pci_region = dev->real_device.regions; int next_cap_pt = 0; + pci_dev->cap.supported = 1; + pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR; pci_dev->cap.length = 0; + pci_dev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; + pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start; + #ifdef KVM_CAP_IRQ_ROUTING #ifdef KVM_CAP_DEVICE_MSI /* Expose MSI capability @@ -1468,9 +1473,10 @@ static int assigned_initfn(struct PCIDevice *pci_dev) dev->h_busnr = dev->host.bus; dev->h_devfn = PCI_DEVFN(dev->host.dev, dev->host.func); - if (pci_enable_capability_support(pci_dev, 0, NULL, - assigned_device_pci_cap_write_config, - assigned_device_pci_cap_init) < 0) + pci_register_capability_handlers(pci_dev, NULL, + assigned_device_pci_cap_write_config); + + if (assigned_device_pci_cap_init(pci_dev) < 0) goto out; /* assign device to guest */ diff --git a/hw/pci.c b/hw/pci.c index 12c47ac..6b2b320 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -787,6 +787,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, config_write = pci_default_write_config; pci_dev->config_read = config_read; pci_dev->config_write = config_write; + pci_dev->cap.config_read = pci_default_cap_read_config; + pci_dev->cap.config_write = pci_default_cap_write_config; bus->devices[devfn] = pci_dev; pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); pci_dev->version_id = 2; /* Current pci device vmstate version */ @@ -1893,35 +1895,21 @@ PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, return dev; } -int pci_enable_capability_support(PCIDevice *pci_dev, - uint32_t config_start, - PCICapConfigReadFunc *config_read, - PCICapConfigWriteFunc *config_write, - PCICapConfigInitFunc *config_init) +void pci_register_capability_handlers(PCIDevice *pdev, + PCICapConfigReadFunc *config_read, + PCICapConfigWriteFunc *config_write) { - if (!pci_dev) - return -ENODEV; - - pci_dev->config[0x06] |= 0x10; // status = capabilities - - if (config_start == 0) - pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR; - else if (config_start >= 0x40 && config_start < 0xff) - pci_dev->cap.start = config_start; - else - return -EINVAL; + if (config_read) { + pdev->cap.config_read = config_read; + } else { + pdev->cap.config_read = pci_default_cap_read_config; + } - if (config_read) - pci_dev->cap.config_read = config_read; - else - pci_dev->cap.config_read = pci_default_cap_read_config; - if (config_write) - pci_dev->cap.config_write = config_write; - else - pci_dev->cap.config_write = pci_default_cap_write_config; - pci_dev->cap.supported = 1; - pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start; - return config_init(pci_dev); + if (config_write) { + pdev->cap.config_write = config_write; + } else { + pdev->cap.config_write = pci_default_cap_write_config; + } } PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) @@ -2045,12 +2033,16 @@ int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id, config[PCI_CAP_LIST_ID] = cap_id; config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; pdev->config[PCI_CAPABILITY_LIST] = offset; - pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; memset(pdev->used + offset, 0xFF, size); /* Make capability read-only by default */ memset(pdev->wmask + offset, 0, size); /* Check capability by default */ memset(pdev->cmask + offset, 0xFF, size); + + pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; + pdev->cap.supported = 1; + pdev->cap.start = pdev->cap.start ? MIN(pdev->cap.start, offset) : offset; + return offset; } @@ -2078,8 +2070,10 @@ void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) memset(pdev->cmask + offset, 0, size); memset(pdev->used + offset, 0, size); - if (!pdev->config[PCI_CAPABILITY_LIST]) + if (!pdev->config[PCI_CAPABILITY_LIST]) { pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; + pdev->cap.start = pdev->cap.length = 0; + } } /* Reserve space for capability at a known offset (to call after load). */ diff --git a/hw/pci.h b/hw/pci.h index 334e928..0712e55 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -87,7 +87,6 @@ typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev, uint32_t address, uint32_t val, int len); typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev, uint32_t address, int len); -typedef int PCICapConfigInitFunc(PCIDevice *pci_dev); typedef struct PCIIORegion { pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ @@ -228,11 +227,9 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type); -int pci_enable_capability_support(PCIDevice *pci_dev, - uint32_t config_start, - PCICapConfigReadFunc *config_read, - PCICapConfigWriteFunc *config_write, - PCICapConfigInitFunc *config_init); +void pci_register_capability_handlers(PCIDevice *pci_dev, + PCICapConfigReadFunc *config_read, + PCICapConfigWriteFunc *config_write); int pci_map_irq(PCIDevice *pci_dev, int pin);