@@ -16509,6 +16509,36 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
gsi_replace (gsi, g, true);
return true;
}
+ /* Even element flavors of vec_mul (signed). */
+ case ALTIVEC_BUILTIN_VMULESB:
+ case ALTIVEC_BUILTIN_VMULESH:
+ /* Even element flavors of vec_mul (unsigned). */
+ case ALTIVEC_BUILTIN_VMULEUB:
+ case ALTIVEC_BUILTIN_VMULEUH:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Odd element flavors of vec_mul (signed). */
+ case ALTIVEC_BUILTIN_VMULOSB:
+ case ALTIVEC_BUILTIN_VMULOSH:
+ /* Odd element flavors of vec_mul (unsigned). */
+ case ALTIVEC_BUILTIN_VMULOUB:
+ case ALTIVEC_BUILTIN_VMULOUH:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
default:
break;
@@ -4,18 +4,18 @@
static void test()
{
- vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
- vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};
- vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
- vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};
- vector unsigned short vusa = {0,1,2,3,4,5,6,7};
- vector unsigned short vusb = {2,3,2,3,2,3,2,3};
- vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};
- vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};
- vector unsigned short vuse, vuso;
- vector signed short vsse, vsso;
- vector unsigned int vuie, vuio;
- vector signed int vsie, vsio;
+ volatile vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+ volatile vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};
+ volatile vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
+ volatile vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};
+ volatile vector unsigned short vusa = {0,1,2,3,4,5,6,7};
+ volatile vector unsigned short vusb = {2,3,2,3,2,3,2,3};
+ volatile vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};
+ volatile vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};
+ volatile vector unsigned short vuse, vuso;
+ volatile vector signed short vsse, vsso;
+ volatile vector unsigned int vuie, vuio;
+ volatile vector signed int vsie, vsio;
vuse = vec_mule (vuca, vucb);
vuso = vec_mulo (vuca, vucb);
new file mode 100644
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with char
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed char
+test3 (vector signed char x, vector signed char y)
+{
+ return vec_mul (x, y);
+}
+
+vector unsigned char
+test6 (vector unsigned char x, vector unsigned char y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]vmulesb" 2 } } */
+/* { dg-final { scan-assembler-times "\[ \t\]vmulosb" 2 } } */
new file mode 100644
@@ -0,0 +1,17 @@
+/* Verify that overloaded built-ins for vec_mul with float
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mvsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]xvmulsp" 1 } } */
+
new file mode 100644
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with float and
+ double inputs for VSX produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -mvsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+ return vec_mul (x, y);
+}
+
+vector double
+test2 (vector double x, vector double y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]xvmulsp" 1 } } */
+/* { dg-final { scan-assembler-times "\[ \t\]xvmuldp" 1 } } */
new file mode 100644
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with int
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed int
+test3 (vector signed int x, vector signed int y)
+{
+ return vec_mul (x, y);
+}
+
+vector unsigned int
+test6 (vector unsigned int x, vector unsigned int y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]vmuluwm" 2 } } */
+
new file mode 100644
@@ -0,0 +1,25 @@
+/* Verify that overloaded built-ins for vec_mul with __int128
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
+
+#include "altivec.h"
+
+vector signed __int128
+test1 (vector signed __int128 x, vector signed __int128 y)
+{
+ return vec_mul (x, y);
+}
+
+vector unsigned __int128
+test2 (vector unsigned __int128 x, vector unsigned __int128 y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 6 } } */
+/* { dg-final { scan-assembler-times "\[ \t\]mulhdu" 2 } } */
new file mode 100644
@@ -0,0 +1,25 @@
+/* Verify that overloaded built-ins for vec_mul with __int128
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_float128_hw_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-maltivec -mvsx -mcpu=power9 -O2" } */
+/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
+
+#include "altivec.h"
+
+vector signed __int128
+test1 (vector signed __int128 x, vector signed __int128 y)
+{
+ return vec_mul (x, y);
+}
+
+vector unsigned __int128
+test2 (vector unsigned __int128 x, vector unsigned __int128 y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]xsmulqp" 2 } } */
new file mode 100644
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with long long
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x, vector signed long long y)
+{
+ return vec_mul (x, y);
+}
+
+vector unsigned long long
+test6 (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 } } */
+
new file mode 100644
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with short
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed short
+test3 (vector signed short x, vector signed short y)
+{
+ return vec_mul (x, y);
+}
+
+vector unsigned short
+test6 (vector unsigned short x, vector unsigned short y)
+{
+ return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]vmladduhm" 2 } } */
+
Hi, This patch implements folding of the vector Multiply built-ins. As part of this patch, I have also marked variables in an existing testcase (mult-even-odd-be-order.c) as volatile, to prevent their being optimized out, which happens once this vector multiply folding was able to occur. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Is this ok for trunk? Thanks, -Will [gcc] 2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c: Add handling for early expansion of vector multiply builtins. [gcc/testsuite] 2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com> * testsuite/gcc.dg/vmx/mult-even-odd-be-order.c : Mark variables as volatile. * testsuite/gcc.target/powerpc/fold-vec-mult-char.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-float.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-int.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-short.c : New.