From patchwork Wed Nov 10 15:45:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: malc X-Patchwork-Id: 70643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D8691B70F4 for ; Thu, 11 Nov 2010 02:46:36 +1100 (EST) Received: from localhost ([127.0.0.1]:48499 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGCsb-0005o7-3z for incoming@patchwork.ozlabs.org; Wed, 10 Nov 2010 10:46:33 -0500 Received: from [140.186.70.92] (port=60289 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGCrt-0005nY-Fp for qemu-devel@nongnu.org; Wed, 10 Nov 2010 10:45:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGCrs-0006OG-Di for qemu-devel@nongnu.org; Wed, 10 Nov 2010 10:45:49 -0500 Received: from fe01x03-cgp.akado.ru ([77.232.31.164]:61568 helo=akado.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGCrs-0006Ma-4A for qemu-devel@nongnu.org; Wed, 10 Nov 2010 10:45:48 -0500 Received: from [10.0.66.9] ([10.0.66.9] verified) by fe01-cgp.akado.ru (CommuniGate Pro SMTP 5.2.13) with ESMTPS id 244379203; Wed, 10 Nov 2010 18:45:44 +0300 Date: Wed, 10 Nov 2010 18:45:37 +0300 (MSK) From: malc X-X-Sender: malc@linmac To: Torbjorn Granlund Subject: Re: [Qemu-devel] Bug report about x86 'bt' insn In-Reply-To: Message-ID: References: <86eiay344b.fsf@shell.gmplib.org> <86wroqmhso.fsf@shell.gmplib.org> <20101106185932.GB26083@nightcrawler> <86bp5xb6y8.fsf@shell.gmplib.org> <8639r9b5wc.fsf@shell.gmplib.org> User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: qemu-devel@nongnu.org, Nathan Froyd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Wed, 10 Nov 2010, malc wrote: > On Wed, 10 Nov 2010, Torbjorn Granlund wrote: > > > malc writes: > > > > All is the keyword here, i doubt that exhaustive search was performed > > furthermore, AMDs documentation (to the best of my knowledge still) > > still maintains that ZF is undefined. > > > > AMD indeed still says undefined in their documentation (as of two hours > > ago). I have asked AMD for a clarification, mainly to make sure they > > are aware of Intel's documentation change. > > > > (I am not certain about what you doubt. As I said, I did not check all > > 2^64 operand values combined all possible bt bit position arguments. I > > believe I have checked all 64-bit x86 processors implementations [two > > generations of Core2, NHM and WSM based Core ix, Via Nano, as well as all > > Athlon64/Opteron generations).) > > I meant all CPU variants. Anyways: tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); @@ -6560,7 +6559,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); break; } - s->cc_op = CC_OP_SARB + ot; + + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_compute_eflags(cpu_cc_src); + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, CC_C); + tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp4); + s->cc_op = CC_OP_EFLAGS; + if (op != 0) { if (mod != 3) gen_op_st_T0_A0(ot + s->mem_index); diff --git a/target-i386/translate.c b/target-i386/translate.c index 7b6e3c2..f416dce 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -6536,8 +6536,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); switch(op) { case 0: - tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); - tcg_gen_movi_tl(cpu_cc_dst, 0); + tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); break; case 1: