From patchwork Wed Nov 10 15:11:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 70640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 9FFD7B70EF for ; Thu, 11 Nov 2010 02:12:16 +1100 (EST) Received: (qmail 29487 invoked by alias); 10 Nov 2010 15:12:09 -0000 Received: (qmail 29473 invoked by uid 22791); 10 Nov 2010 15:12:06 -0000 X-SWARE-Spam-Status: No, hits=-6.0 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 10 Nov 2010 15:12:00 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAAFBxmI003279 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 10 Nov 2010 10:11:59 -0500 Received: from [10.36.5.38] (vpn1-5-38.ams2.redhat.com [10.36.5.38]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id oAAFBv1T024088; Wed, 10 Nov 2010 10:11:57 -0500 Message-ID: <4CDAB63C.2010706@redhat.com> Date: Wed, 10 Nov 2010 15:11:56 +0000 From: Nick Clifton User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.12) Gecko/20101103 Fedora/1.0-0.33.b2pre.fc14 Thunderbird/3.1.6 MIME-Version: 1.0 To: Jeff Law CC: rth@redhat.com, aoliva@redhat.com, gcc-patches@gcc.gnu.org Subject: Re: RFA: MN10300: Add redundant comparison elimination pass References: <4CDAAE38.6000202@redhat.com> <4CDAB0B1.8010700@redhat.com> <4CDAB29D.8020906@redhat.com> In-Reply-To: <4CDAB29D.8020906@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi Jeff, > I'd like to see us DTRT, otherwise I suspect this will get dropped on > the floor. OK, I'll do that. > I'd look to catch add/sub and the logicals; anything beyond those > probably isn't worth the headache. Sure - I'll have a go at coding this now. For the record I am attaching the latest version of the reorg version of the patch with fixes for all the other points raised by various reviewers. Cheers Nick Index: gcc/config/mn10300/mn10300.c =================================================================== --- gcc/config/mn10300/mn10300.c (revision 166474) +++ gcc/config/mn10300/mn10300.c (working copy) @@ -2403,6 +2403,128 @@ /* Extract the latency value from the timings attribute. */ return timings < 100 ? (timings % 10) : (timings % 100); } + +static void +scan_for_redundant_compares (void) +{ + rtx cur_insn; + + /* Look for this sequence: + + (set (reg X) (arith_op (...))) + (set (reg CC) (compare (reg X) (const_int 0))) + (set (pc) (if_then_else (EQ|NE (...)) (...) (...))) + + And remove the compare as the flags in the + EPSW register will already be correctly set. */ + for (cur_insn = get_insns (); cur_insn != NULL; cur_insn = NEXT_INSN (cur_insn)) + { + rtx pattern; + + if (! INSN_P (cur_insn)) + continue; + + pattern = PATTERN (cur_insn); + + if (GET_CODE (pattern) == SET + && GET_CODE (SET_SRC (pattern)) == COMPARE + /* Paranoia checks: */ + && REG_P (SET_DEST (pattern)) + && REGNO (SET_DEST (pattern)) == CC_REG + && REG_P (XEXP (SET_SRC (pattern), 0)) + /* Normal checks: */ + && CONST_INT_P (XEXP (SET_SRC (pattern), 1)) + && INTVAL (XEXP (SET_SRC (pattern), 1)) == 0) + { + rtx prev_insn, branch, condition; + unsigned int compare_reg; + + /* FIXME: We should scan backwards until the first ESPW + setter or clobber insn is found (or the beginning of + the block). At the moment we just look back one insn. */ + prev_insn = prev_nonnote_insn (cur_insn); + + if (prev_insn == NULL || ! INSN_P (prev_insn)) + continue; + + /* An UNSPEC might be an LIW insn which will not set the + condition code flags in a way that we currently expect. */ + if (GET_CODE (PATTERN (prev_insn)) == UNSPEC) + continue; + + if (GET_CODE (PATTERN (prev_insn)) != PARALLEL + || XVECLEN (PATTERN (prev_insn), 0) != 2 + || GET_CODE (XVECEXP (PATTERN (prev_insn), 0, 0)) != SET) + continue; + + compare_reg = REGNO (XEXP (SET_SRC (pattern), 0)); + pattern = XVECEXP (PATTERN (prev_insn), 0, 0); + + if (! REG_P (SET_DEST (pattern)) + || REGNO (SET_DEST (pattern)) != compare_reg) + continue; + + branch = next_nonnote_insn (cur_insn); + if (branch == NULL || ! JUMP_P (branch) + || GET_CODE (PATTERN (branch)) != SET + || GET_CODE (SET_SRC (PATTERN (branch))) != IF_THEN_ELSE) + continue; + condition = XEXP (SET_SRC (PATTERN (branch)), 0); + + switch (GET_CODE (condition)) + { + case EQ: + case NE: + break; + default: + continue; + } + + /* Adding 1 or 4 to an address register results in an + INC/INC4 instruction that doesn't set the flags. */ + if (GET_CODE (SET_SRC (pattern)) == PLUS + && REG_P (SET_DEST (pattern)) + && REGNO (SET_DEST (pattern)) >= FIRST_ADDRESS_REGNUM + && REGNO (SET_DEST (pattern)) <= LAST_ADDRESS_REGNUM + && REG_P (XEXP (SET_SRC (pattern), 0)) + && REGNO (XEXP (SET_SRC (pattern), 0)) == REGNO (SET_DEST (pattern)) + && CONST_INT_P (XEXP (SET_SRC (pattern), 1)) + && (INTVAL (XEXP (SET_SRC (pattern), 1)) == 1 + || INTVAL (XEXP (SET_SRC (pattern), 1)) == 4)) + continue; + + switch (GET_CODE (SET_SRC (pattern))) + { + case PLUS: + case MINUS: + case MULT: +#if 0 + /* Some alternatives in the AND pattern use EXTBU which does + not set the flags. Hence a CMP following an AND might be + needed. */ + case AND: +#endif + case XOR: + case NOT: + case ASHIFT: + case LSHIFTRT: + case ASHIFTRT: + delete_insn (cur_insn); + break; + default: + break; + } + } + } +} + +/* Implements TARGET_MACHINE_DEPENDENT_REORG. */ + +static void +mn10300_reorg (void) +{ + scan_for_redundant_compares (); +} /* Initialize the GCC target structure. */ @@ -2481,4 +2603,7 @@ #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost +#undef TARGET_MACHINE_DEPENDENT_REORG +#define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg + struct gcc_target targetm = TARGET_INITIALIZER;