diff mbox

[U-Boot,PATCHv2,1/2] ARMv8/fsl-layerscape: Correct the OCRAM size

Message ID 1481879746-35071-1-git-send-email-Zhiqiang.Hou@nxp.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Z.Q. Hou Dec. 16, 2016, 9:15 a.m. UTC
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - New patch

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 +++++---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h    | 8 ++++----
 2 files changed, 9 insertions(+), 7 deletions(-)

Comments

York Sun Dec. 16, 2016, 4:39 p.m. UTC | #1
On 12/16/2016 01:29 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> The real size of OCRAM is 128KiB, so correct the size of OCRAM.
> And OCRAM reserved 2MiB space, then add a new macro to describe
> it, which is used for MMU setup.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - New patch
>
>  arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 +++++---
>  arch/arm/include/asm/arch-fsl-layerscape/cpu.h    | 8 ++++----
>  2 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index c50894a..8e2eea3 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -28,8 +28,9 @@
>  #define CONFIG_FSL_TZASC_400
>  #endif
>
> -#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
> -#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
> +#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
> +#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
> +#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */



>
>  /* DDR */
>  #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
> @@ -137,7 +138,8 @@
>  #elif defined(CONFIG_FSL_LSCH2)
>  #define CONFIG_SYS_FSL_SEC_COMPAT		5
>  #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
> -#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */
> +#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */


Zhiqiang,

The history behind the OCRAM size is page table size. We started from 
fixed table. 2MB was the page granule size to avoid too many tables. 
With now MMU code, we can use 4KB page granule to get rid of this macro, 
but I'd rather not to create a new table just for this purpose.

I see you want to use the real OCRAM size to initialize it. Why don't 
you use a new macro like SYS_FSL_OCRAM_REAL_SIZE so you don't have to 
change other code. Or better use Kconfig option for the new macro.

York
Z.Q. Hou Dec. 19, 2016, 2:42 a.m. UTC | #2
Hi York,

Thanks a lot for your comments!

> -----Original Message-----

> From: york sun

> Sent: 2016年12月17日 0:39

> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; Prabhakar

> Kushwaha <prabhakar.kushwaha@nxp.com>; Ruchika Gupta

> <ruchika.gupta@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Pratiyush

> Srivastava <pratiyush.srivastava@nxp.com>

> Subject: Re: [PATCHv2 1/2] ARMv8/fsl-layerscape: Correct the OCRAM size

> 

> On 12/16/2016 01:29 AM, Zhiqiang Hou wrote:

> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

> >

> > The real size of OCRAM is 128KiB, so correct the size of OCRAM.

> > And OCRAM reserved 2MiB space, then add a new macro to describe it,

> > which is used for MMU setup.

> >

> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

> > ---

> > V2:

> >  - New patch

> >

> >  arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 +++++---

> >  arch/arm/include/asm/arch-fsl-layerscape/cpu.h    | 8 ++++----

> >  2 files changed, 9 insertions(+), 7 deletions(-)

> >

> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h

> > b/arch/arm/include/asm/arch-fsl-layerscape/config.h

> > index c50894a..8e2eea3 100644

> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h

> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h

> > @@ -28,8 +28,9 @@

> >  #define CONFIG_FSL_TZASC_400

> >  #endif

> >

> > -#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */

> > -#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */

> > +#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */

> > +#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */

> > +#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */

> 

> 

> 

> >

> >  /* DDR */

> >  #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)

> > @@ -137,7 +138,8 @@

> >  #elif defined(CONFIG_FSL_LSCH2)

> >  #define CONFIG_SYS_FSL_SEC_COMPAT		5

> >  #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial

> RAM */

> > -#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */

> > +#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */

> 

> 

> Zhiqiang,

> 

> The history behind the OCRAM size is page table size. We started from fixed

> table. 2MB was the page granule size to avoid too many tables.

> With now MMU code, we can use 4KB page granule to get rid of this macro,

> but I'd rather not to create a new table just for this purpose.

> 

> I see you want to use the real OCRAM size to initialize it. Why don't you use a

> new macro like SYS_FSL_OCRAM_REAL_SIZE so you don't have to change

> other code. Or better use Kconfig option for the new macro.

> 


The OCRAM_SIZE and OCRAM_REAL_SIZE, I afraid it is confusing.
I think the OCRAM size and OCRAM base are hardware attributes and it's better to stay them in the config.h.

Thanks,
Zhiqiang
York Sun Jan. 19, 2017, 5:29 p.m. UTC | #3
On 12/16/2016 01:29 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> The real size of OCRAM is 128KiB, so correct the size of OCRAM.
> And OCRAM reserved 2MiB space, then add a new macro to describe
> it, which is used for MMU setup.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - New patch
>

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index c50894a..8e2eea3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -28,8 +28,9 @@ 
 #define CONFIG_FSL_TZASC_400
 #endif
 
-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* DDR */
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
@@ -137,7 +138,8 @@ 
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
 
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
 #define CONFIG_SYS_FSL_ESDHC_BE
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index a97be5c..4ea4aea 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -93,7 +93,7 @@  static struct mm_region early_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
@@ -140,7 +140,7 @@  static struct mm_region early_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
@@ -178,7 +178,7 @@  static struct mm_region final_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
@@ -280,7 +280,7 @@  static struct mm_region final_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,