| Message ID | A614194ED15B4844BC4C9FB7F21FCD9222538F75@HHMAIL01.hh.imgtec.org |
|---|---|
| State | New |
| Headers | show |
> -----Original Message----- > From: Toma Tabacu [mailto:Toma.Tabacu@imgtec.com] > Sent: Thursday, December 15, 2016 9:51 AM > To: gcc-patches@gcc.gnu.org > Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>; Moore, > Catherine <Catherine_Moore@mentor.com> > Subject: [PATCH, testsuite] MIPS: Relax instruction order check in msa- > builtins.c. > > Hi, > > The 32-bit insert.d case in msa-builtins.c is failing with O2 and Os > because > the order of the emitted instructions is slightly different compared to > the > other optimization levels. > > This patch tweaks the regular expression for 32-bit insert.d to accept > the > alternate instruction order. > > Tested with mips-mti-elf. > > Regards, > Toma > > gcc/testsuite/ChangeLog: > > * gcc.target/mips/msa-builtins.c (dg-final): Tweak regex for the > 32-bit > insert.d case. Please change to: * gcc.target/mips-msa-builtins.c (msa_insert_d): Tweak expected output. Okay with that change. Thanks, Catherine > > diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins.c > b/gcc/testsuite/gcc.target/mips/msa-builtins.c > index 6db3d66..a679f06 100644 > --- a/gcc/testsuite/gcc.target/mips/msa-builtins.c > +++ b/gcc/testsuite/gcc.target/mips/msa-builtins.c > @@ -481,7 +481,7 @@ > /* { dg-final { scan-assembler-times > "msa_insert_h:.*insert\\.h.*msa_insert_h" 1 } } */ > /* { dg-final { scan-assembler-times > "msa_insert_w:.*insert\\.w.*msa_insert_w" 1 } } */ > /* { dg-final { scan-assembler-times > "msa_insert_d:.*insert\\.d.*msa_insert_d" 1 { target mips64 } } } */ > -/* { dg-final { scan-assembler-times > "msa_insert_d:.*sra.*insert.w.*insert.w.*msa_insert_d" 1 { target {! > mips64 } } } } */ > +/* { dg-final { scan-assembler > "msa_insert_d:.*(sra.*insert.w.*insert.w|insert.w.*sra.*insert.w).*ms > a_insert_d" { target {! mips64 } } } } */ > /* { dg-final { scan-assembler-times > "msa_insve_b:.*insve\\.b.*msa_insve_b" 1 } } */ > /* { dg-final { scan-assembler-times > "msa_insve_h:.*insve\\.h.*msa_insve_h" 1 } } */ > /* { dg-final { scan-assembler-times > "msa_insve_w:.*insve\\.w.*msa_insve_w" 1 } } */
> Catherine Moore writes: > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/msa-builtins.c (dg-final): Tweak regex for the > > 32-bit > > insert.d case. > > Please change to: > * gcc.target/mips-msa-builtins.c (msa_insert_d): Tweak expected > output. > > Okay with that change. > Thanks, > Catherine > Committed as r243848. Regards, Toma
diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins.c b/gcc/testsuite/gcc.target/mips/msa-builtins.c index 6db3d66..a679f06 100644 --- a/gcc/testsuite/gcc.target/mips/msa-builtins.c +++ b/gcc/testsuite/gcc.target/mips/msa-builtins.c @@ -481,7 +481,7 @@ /* { dg-final { scan-assembler-times "msa_insert_h:.*insert\\.h.*msa_insert_h" 1 } } */ /* { dg-final { scan-assembler-times "msa_insert_w:.*insert\\.w.*msa_insert_w" 1 } } */ /* { dg-final { scan-assembler-times "msa_insert_d:.*insert\\.d.*msa_insert_d" 1 { target mips64 } } } */ -/* { dg-final { scan-assembler-times "msa_insert_d:.*sra.*insert.w.*insert.w.*msa_insert_d" 1 { target {! mips64 } } } } */ +/* { dg-final { scan-assembler "msa_insert_d:.*(sra.*insert.w.*insert.w|insert.w.*sra.*insert.w).*msa_insert_d" { target {! mips64 } } } } */ /* { dg-final { scan-assembler-times "msa_insve_b:.*insve\\.b.*msa_insve_b" 1 } } */ /* { dg-final { scan-assembler-times "msa_insve_h:.*insve\\.h.*msa_insve_h" 1 } } */ /* { dg-final { scan-assembler-times "msa_insve_w:.*insve\\.w.*msa_insve_w" 1 } } */