diff mbox

[SPARC] Adjust T constraint

Message ID 2395674.fsfTfpvWjH@polaris
State New
Headers show

Commit Message

Eric Botcazou Dec. 12, 2016, 7:57 a.m. UTC 
The main purpose of the T constraint is to make sure that a memory reference 
is aligned on a 64-bit boundary in 32-bit mode.  But define_memory_constraint 
is not appropriate for such a constraint, because reload may think that it can 
satisfy it by reloading the address, which is of course wrong; this apparently 
never happens with old reload, but does with LRA and is responsible for the 
last couple of regressions in the testsuite in 32-bit mode.

Tested on SPARC/Solaris w/ and w/o -mlra, applied on the mainline.


2016-12-12  Eric Botcazou  <ebotcazou@adacore.com>

	* config/sparc/constraints.md (T): Use special memory constraint.
	(U): Minor tweak.
	(W): Add TARGET_ARCH64 test.
	* config/sparc/sparc.md (*movdi_insn_sp32): Replace 'W' with 'T'.
	(*movdf_insn_sp32): Likewise.
	(*mov<VM64:mode>_insn_sp32): Likewise.  Replace 'e' with 'f' in
	conjunction with offsettable memory references.
diff mbox

Patch

Index: config/sparc/constraints.md
===================================================================
--- config/sparc/constraints.md	(revision 243513)
+++ config/sparc/constraints.md	(working copy)
@@ -128,11 +128,11 @@  (define_constraint "S"
  (and (match_code "const_double")
       (match_test "fp_high_losum_p (op)")))
 
-;; Not needed in 64-bit mode
-(define_memory_constraint "T"
+;; We need a special memory constraint because of the alignment requirement
+(define_special_memory_constraint "T"
  "Memory reference whose address is aligned to 8-byte boundary"
- (and (match_test "TARGET_ARCH32")
-      (match_code "mem")
+ (and (match_code "mem")
+      (match_test "TARGET_ARCH32")
       (match_test "memory_ok_for_ldd (op)")))
 
 ;; This awkward register constraint is necessary because it is not
@@ -174,16 +174,17 @@  (define_memory_constraint "T"
 ;; reg_class_for_constraint, and checks it against NO_REGS.
 (define_constraint "U"
  "Pseudo-register or hard even-numbered integer register"
- (and (match_test "TARGET_ARCH32")
-      (match_code "reg")
+ (and (match_code "reg")
       (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
 	   (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
+      (match_test "TARGET_ARCH32")
       (match_test "register_ok_for_ldd (op)")))
 
-;; Equivalent to 'T' but available in 64-bit mode
+;; Equivalent to 'T' but in 64-bit mode without alignment requirement
 (define_memory_constraint "W"
  "Memory reference for 'e' constraint floating-point register"
  (and (match_code "mem")
+      (match_test "TARGET_ARCH64")
       (match_test "memory_ok_for_ldd (op)")))
 
 (define_memory_constraint "w"
Index: config/sparc/sparc.md
===================================================================
--- config/sparc/sparc.md	(revision 243513)
+++ config/sparc/sparc.md	(working copy)
@@ -1705,9 +1705,9 @@  (define_expand "movdi"
 
 (define_insn "*movdi_insn_sp32"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-			    "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e,  r,?*f,?*e,?W,*b,*b")
+			    "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e,  r,?*f,?*e,?T,*b,*b")
         (match_operand:DI 1 "input_operand"
-			    " J,J,T,U,o,r,i,r,  T,*f,  o,*f, *e, *e,?*f,  r,  W,*e, J, P"))]
+			    " J,J,T,U,o,r,i,r,  T,*f,  o,*f, *e, *e,?*f,  r,  T,*e, J, P"))]
   "TARGET_ARCH32
    && (register_operand (operands[0], DImode)
        || register_or_zero_operand (operands[1], DImode))"
@@ -2336,9 +2336,9 @@  (define_expand "movdf"
 
 (define_insn "*movdf_insn_sp32"
   [(set (match_operand:DF 0 "nonimmediate_operand"
-			    "=T,o,b,b,e,e,*r, f,  e,W,U,T,  f,o, *r,*r, o")
+			    "=T,o,b,b,e,e,*r, f,  e,T,U,T,  f,o, *r,*r, o")
 	(match_operand:DF 1 "input_operand"
-			    " G,G,G,C,e,e, f,*r,W#F,e,T,U,o#F,f,*rF, o,*r"))]
+			    " G,G,G,C,e,e, f,*r,T#F,e,T,U,o#F,f,*rF, o,*r"))]
   "TARGET_ARCH32
    && (register_operand (operands[0], DFmode)
        || register_or_zero_or_all_ones_operand (operands[1], DFmode))"
@@ -8543,9 +8543,9 @@  (define_insn "*mov<VM64:mode>_insn_sp64"
 
 (define_insn "*mov<VM64:mode>_insn_sp32"
   [(set (match_operand:VM64 0 "nonimmediate_operand"
-			      "=T,o,e,e,e,*r, f,e,W,U,T,e,o,*r,*r, o")
+			      "=T,o,e,e,e,*r, f,e,T,U,T,f,o,*r,*r, o")
 	(match_operand:VM64 1 "input_operand"
-			      " Y,Y,Y,Z,e, f,*r,W,e,T,U,o,e,*r, o,*r"))]
+			      " Y,Y,Y,Z,e, f,*r,T,e,T,U,o,f,*r, o,*r"))]
   "TARGET_VIS
    && TARGET_ARCH32
    && (register_operand (operands[0], <VM64:MODE>mode)