Patchwork pdp11: fix wrong code

login
register
mail settings
Submitter Paul Koning
Date Nov. 9, 2010, 1:15 a.m.
Message ID <086E06BA-0C4E-433C-A172-C9AA17BA466D@dell.com>
Download mbox | patch
Permalink /patch/70484/
State New
Headers show

Comments

Paul Koning - Nov. 9, 2010, 1:15 a.m.
This is another wrong-code fix, in logical right shift.  The original code tried to optimize the case for shift by 1, but ended up unconditionally shifting by 1 even if the request was for a different shift.

Tested by build and inspection of the output.  Committed.

	paul

ChangeLog:

2010-11-08  Paul Koning  <ni1d@arrl.net>

	* config/pdp11/pdp11.md (lshrsi3, lshrhi3): Fix wrong code.

Patch

Index: config/pdp11/pdp11.md
===================================================================
--- config/pdp11/pdp11.md	(revision 166467)
+++ config/pdp11/pdp11.md	(working copy)
@@ -849,7 +849,7 @@ 
   [(set_attr "length" "2,4")])
 
 ;; lsr
-(define_insn "" 
+(define_insn "lsrhi1" 
   [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q")
 	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0")
 		   (const_int 1)))]
@@ -857,7 +857,7 @@ 
   "clc\;ror %0"
   [(set_attr "length" "2,4")])
 
-(define_insn "lshrsi3"
+(define_insn "lsrsi1"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
                    (const_int 1)))]
@@ -880,6 +880,36 @@ 
 }
   [(set_attr "length" "10")])
 
+(define_expand "lshrsi3"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "0")
+   (match_operand:HI 2 "general_operand" "")]
+  ""
+  "
+{
+  rtx r;
+
+  if (!TARGET_40_PLUS &&
+      (GET_CODE (operands[2]) != CONST_INT ||
+       (unsigned) INTVAL (operands[2]) > 3))
+    FAIL;
+  emit_insn (gen_lsrsi1 (operands[0], operands[1]));
+  if (GET_CODE (operands[2]) != CONST_INT)
+    {
+      r = gen_reg_rtx (HImode);
+      emit_insn (gen_subhi3 (r, operands [2], GEN_INT (1)));
+      emit_insn (gen_ashrsi3 (operands[0], operands[0], r));
+    }
+  else if ((unsigned) INTVAL (operands[2]) != 1)
+    {
+      emit_insn (gen_ashlsi3 (operands[0], operands[0],
+                              GEN_INT (1 - INTVAL (operands[2]))));
+    }
+  DONE;
+}
+"
+)
+
 ;; shift is by arbitrary count is expensive, 
 ;; shift by one cheap - so let's do that, if
 ;; space doesn't matter
@@ -996,14 +1026,36 @@ 
   operands[2] = negate_rtx (HImode, operands[2]);
 }")
 
-;;;;- logical shift instructions
-;;(define_insn "lshrsi3"
-;;  [(set (match_operand:HI 0 "register_operand" "=r")
-;;	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-;;		     (match_operand:HI 2 "general_operand" "rI")))]
-;;  ""
-;;  "srl %0,%2")
+(define_expand "lshrhi3"
+  [(match_operand:HI 0 "register_operand" "")
+   (match_operand:HI 1 "register_operand" "")
+   (match_operand:HI 2 "general_operand" "")]
+  ""
+  "
+{
+  rtx r;
 
+  if (!TARGET_40_PLUS &&
+      (GET_CODE (operands[2]) != CONST_INT ||
+       (unsigned) INTVAL (operands[2]) > 3))
+    FAIL;
+  emit_insn (gen_lsrhi1 (operands[0], operands[1]));
+  if (GET_CODE (operands[2]) != CONST_INT)
+    {
+      r = gen_reg_rtx (HImode);
+      emit_insn (gen_subhi3 (r, operands [2], GEN_INT (1)));
+      emit_insn (gen_ashrhi3 (operands[0], operands[0], r));
+    }
+  else if ((unsigned) INTVAL (operands[2]) != 1)
+    {
+      emit_insn (gen_ashlhi3 (operands[0], operands[0],
+                              GEN_INT (1 - INTVAL (operands[2]))));
+    }
+  DONE;
+}
+"
+)
+
 ;; absolute 
 
 (define_insn "absdf2"