From patchwork Fri Nov 5 12:22:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 70259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id DCC311007D1 for ; Fri, 5 Nov 2010 23:23:17 +1100 (EST) Received: (qmail 623 invoked by alias); 5 Nov 2010 12:23:13 -0000 Received: (qmail 614 invoked by uid 22791); 5 Nov 2010 12:23:11 -0000 X-SWARE-Spam-Status: No, hits=-1.2 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, TW_AV, TW_VZ, TW_ZJ, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 05 Nov 2010 12:22:56 +0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 05 Nov 2010 05:22:55 -0700 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by orsmga002.jf.intel.com with ESMTP; 05 Nov 2010 05:22:54 -0700 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id A994B207F0; Fri, 5 Nov 2010 05:22:54 -0700 (PDT) Date: Fri, 5 Nov 2010 05:22:54 -0700 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: PATCH: Check 256bit AVX register in move expanders Message-ID: <20101105122254.GA21908@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch checks 256bit AVX register in move expanders. OK for trunk? Thanks. H.J. --- gcc/ 2010-11-05 H.J. Lu Uros Bizjak * config/i386/i386.c (ix86_expand_move): Set use_avx256_p if 256bit AVX register is used. (ix86_expand_vector_move_misalign): Likewise. (ix86_expand_vector_move): Replace use_avx256_p with VALID_AVX256_REG_MODE. gcc/testsuite/ 2010-11-05 H.J. Lu * gcc.target/i386/avx-vzeroupper-19.c: New. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3558899..00febba 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15000,6 +15000,9 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) rtx op0, op1; enum tls_model model; + if (VALID_AVX256_REG_MODE (mode)) + cfun->machine->use_avx256_p = true; + op0 = operands[0]; op1 = operands[1]; @@ -15144,7 +15147,7 @@ ix86_expand_vector_move (enum machine_mode mode, rtx operands[]) rtx op0 = operands[0], op1 = operands[1]; unsigned int align = GET_MODE_ALIGNMENT (mode); - if (use_avx256_p (mode, NULL_TREE)) + if (VALID_AVX256_REG_MODE (mode)) cfun->machine->use_avx256_p = true; /* Force constants other than zero into memory. We do not know how @@ -15253,6 +15256,9 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { rtx op0, op1, m; + if (VALID_AVX256_REG_MODE (mode)) + cfun->machine->use_avx256_p = true; + op0 = operands[0]; op1 = operands[1]; diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c new file mode 100644 index 0000000..602de87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mtune=generic -dp" } */ + +void feat_s3_cep_dcep (int cepsize_used, float **mfc, float **feat) +{ + float *f; + float *w, *_w; + int i; + __builtin_memcpy (feat[0], mfc[0], cepsize_used * sizeof(float)); + f = feat[0] + cepsize_used; + w = mfc[2]; + _w = mfc[-2]; + for (i = 0; i < cepsize_used; i++) + f[i] = w[i] - _w[i]; +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */