Patchwork [ARM] Rename f_load and f_store attributes to f_fpa_load and f_fpa_store .

login
register
mail settings
Submitter Ramana Radhakrishnan
Date Nov. 5, 2010, 7:58 a.m.
Message ID <AANLkTikXAZ91_DzhReo2CnqgOap6jeybP6WRfG-Duw0j@mail.gmail.com>
Download mbox | patch
Permalink /patch/70248/
State New
Headers show

Comments

Ramana Radhakrishnan - Nov. 5, 2010, 7:58 a.m.
Hi,

There is scope for confusing the `f_load' and `f_store' with the
`f_load[s,d]'  and the f_store[s/d] type attributes in the ARM
backend.  The f_load and f_store are typically for the FPA and must be
used as such. Recent pipeline descriptions as well as some patterns in
the VFP machine description end up using `f_load and f_store` in the
pipeline descriptions ignoring the f_loads and f_stores attributes in
particular. Some of the VFP patterns use f_load while others use
f_load[s,d] and this usage isn't consistent in the backend.

Richard suggested that we rename these types to f_fpa_load and
f_fpa_store rather than just updating comments and the appropriate
uses since it ends up flushing out other interesting uses of such
attributes.

This patch attempts to rectify the situation by :

1. Renaming f_load and f_store to their f_fpa_load and f_fpa_store variants.
2. Replacing f_load and f_store in the VFP machine descriptions with
appropriate f_load[s,d] and f_store[s,d] attribute values. Given that
f_load and f_store were typically for the FPA having patterns in the
VFP backend that have these values set on insn types is not consistent
usage.
3. Renaming f_load and f_store in fpa.md to f_fpa_load and f_fpa_store.
4. Remove use of f_load in A5 description.
5. Correct use of f_load in the M4 pipeline description.

Currently testing cross for v7-a eabi and qemu .

Ok to commit to trunk ?

Cheers
Ramana



    * config/arm/arm.md (define_attr type): Rename f_load
       and f_store to f_fpa_load and f_fpa_store. Update.
       (write_conflict): Deal with rename fallout.
       (*push_fp_multi): Likewise.
    * config/arm/fpa.md (f_load): Use f_fpa_load.
       (f_store): Use f_fpa_store.
       (*movsf_fpa): Likewise.
       (*movdf_fpa): Likewise.
       (*movxf_fpa): Likewise.
       (*thumb2_movsf_fpa): Likewise.
       (*thumb2_movdf_fpa): Likewise.
       (*thumb2_movxf_fpa): Likewise.
    * config/arm/vfp.md (*thumb2_movdf_vfp): Fix attribute to
       f_loadd and f_stored.
       (*thumb2_movdi_vfp): Likewise.
       (*thumb2_movsf_vfp): Fix attribute to f_loads.
       (*thumb2_movsi_vfp): Likewise.
   * config/arm/cortex-m4-fpu.md (cortex_m4_f_load):
      Use f_loads instead of f_load.
   * config/arm/cortex-a5.md (cortex_a5_f_loads): Remove f_load.
Ramana Radhakrishnan - Jan. 18, 2011, 2:57 p.m.
> Ok to commit to trunk ?

Ping or should this wait for stage1 ?


cheers
Ramana

Patch

From 0f9e49132a5215c65eb59aff6606d62bd9cde693 Mon Sep 17 00:00:00 2001
From: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Date: Thu, 4 Nov 2010 05:30:02 +0000
Subject: [PATCH 1/3] 	* config/arm/arm.md (define_attr type): Rename f_load
 	and f_store to f_fpa_load and f_fpa_store. Update.
 	(write_conflict): Deal with rename fallout.
 	(*push_fp_multi): Likewise.
 	* config/arm/fpa.md (define_insn_reservation f_load): Use f_fpa_load.
 	(define_insn_reservation f_store): Use f_fpa_store.
 	(*movsf_fpa): Likewise.
 	(*movdf_fpa): Likewise.
 	(*movxf_fpa): Likewise.
 	(*thumb2_movsf_fpa): Likewise.
 	(*thumb2_movdf_fpa): Likewise.
 	(*thumb2_movxf_fpa): Likewise.
 	* config/arm/vfp.md (*thumb2_movdf_vfp): Fix attribute to
 	f_loadd and f_stored.
 	(*thumb2_movdi_vfp): Likewise.
 	(*thumb2_movsf_vfp): Fix attribute to f_loads.
 	(*thumb2_movsi_vfp): Likewise.

---
 arm.md |   14 +++++++-------
 fpa.md |   16 ++++++++--------
 vfp.md |    8 ++++----
 3 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/arm.md b/arm.md
index 889b86f..394772b 100644
--- a/arm.md
+++ b/arm.md
@@ -299,10 +299,10 @@ 
 ; ffarith	Fast floating point arithmetic (2 cycle)
 ; float_em	a floating point arithmetic operation that is normally emulated
 ;		even on a machine with an fpa.
-; f_load	a floating point load from memory
-; f_store	a floating point store to memory
-; f_load[sd]	single/double load from memory
-; f_store[sd]	single/double store to memory
+; f_fpa_load	a floating point load from memory. Only for the FPA.
+; f_fpa_store	a floating point store to memory. Only for the FPA.
+; f_load[sd]	A single/double load from memory. Used for VFP unit.
+; f_store[sd]	A single/double store to memory. Used for VFP unit.
 ; f_flag	a transfer of co-processor flags to the CPSR
 ; f_mem_r	a transfer of a floating point register to a real reg via mem
 ; r_mem_f	the reverse of f_mem_r
@@ -326,7 +326,7 @@ 
 ;
 
 (define_attr "type"
-	"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
+	"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
 	(if_then_else 
 	 (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
 	 (const_string "mult")
@@ -450,7 +450,7 @@ 
 ; to stall the processor.  Used with model_wbuf above.
 (define_attr "write_conflict" "no,yes"
   (if_then_else (eq_attr "type"
-		 "block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load1")
+		 "block,float_em,f_fpa_load,f_fpa_store,f_mem_r,r_mem_f,call,load1")
 		(const_string "yes")
 		(const_string "no")))
 
@@ -10280,7 +10280,7 @@ 
     output_asm_insn (pattern, operands);
     return \"\";
   }"
-  [(set_attr "type" "f_store")]
+  [(set_attr "type" "f_fpa_store")]
 )
 
 ;; Special patterns for dealing with the constant pool
diff --git a/fpa.md b/fpa.md
index 515de43..6e6dd8d 100644
--- a/fpa.md
+++ b/fpa.md
@@ -83,11 +83,11 @@ 
   "core+fpa*2")
 
 (define_insn_reservation "f_load" 3
-  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load"))
+  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_load"))
   "fpa_mem+core*3")
 
 (define_insn_reservation "f_store" 4
-  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store"))
+  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_store"))
   "core*4")
 
 (define_insn_reservation "r_mem_f" 6
@@ -545,7 +545,7 @@ 
   [(set_attr "length" "4,4,4,4,8,8,4,4,4")
    (set_attr "predicable" "yes")
    (set_attr "type"
-	 "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1")
+	 "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
    (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
    (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
 )
@@ -580,7 +580,7 @@ 
   [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
    (set_attr "predicable" "yes")
    (set_attr "type"
-    "load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
+    "load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
    (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
    (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
 )
@@ -609,7 +609,7 @@ 
   "
   [(set_attr "length" "4,4,4")
    (set_attr "predicable" "yes")
-   (set_attr "type" "ffarith,f_load,f_store")]
+   (set_attr "type" "ffarith,f_fpa_load,f_fpa_store")]
 )
 
 ;; stfs/ldfs always use a conditional infix.  This works around the
@@ -635,7 +635,7 @@ 
    (set_attr "ce_count" "1,1,1,1,2,2,1,1,1")
    (set_attr "predicable" "yes")
    (set_attr "type"
-	 "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1")
+	 "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
    (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
    (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,0,*")]
 )
@@ -669,7 +669,7 @@ 
   "
   [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
    (set_attr "type"
-    "load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
+    "load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
    (set_attr "pool_range" "*,*,*,*,4092,*,*,1024,*,*,*")
    (set_attr "neg_pool_range" "*,*,*,*,0,*,*,1020,*,*,*")]
 )
@@ -698,7 +698,7 @@ 
     }
   "
   [(set_attr "length" "4,4,4,4,8,8,12")
-   (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")
+   (set_attr "type" "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*")
    (set_attr "pool_range" "*,*,1024,*,*,*,*")
    (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
 )
diff --git a/vfp.md b/vfp.md
index 4e7b801..4c6a76b 100644
--- a/vfp.md
+++ b/vfp.md
@@ -123,7 +123,7 @@ 
     }
   "
   [(set_attr "predicable" "yes")
-   (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
+   (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
    (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
@@ -199,7 +199,7 @@ 
       abort ();
     }
   "
-  [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
+  [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
    (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
 			       (eq_attr "alternative" "5")
 				(if_then_else
@@ -390,7 +390,7 @@ 
   "
   [(set_attr "predicable" "yes")
    (set_attr "type"
-     "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
+     "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
    (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
@@ -477,7 +477,7 @@ 
     }
   "
   [(set_attr "type"
-     "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
+     "r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*")
    (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
 			       (eq_attr "alternative" "7")
 				(if_then_else
-- 
1.7.1