Patchwork doc: add pdp11 machine constraints

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Submitter Paul Koning
Date Nov. 5, 2010, 1:03 a.m.
Message ID <56BF3981-59C7-4930-A64A-8CFF7508AFD7@dell.com>
Download mbox | patch
Permalink /patch/70203/
State New
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Comments

Paul Koning - Nov. 5, 2010, 1:03 a.m.
On Nov 4, 2010, at 8:45 PM, Joseph S. Myers wrote:

> On Thu, 4 Nov 2010, Paul Koning wrote:
> 
>> +Odd numbered general registers (R1, R3, R5).  These are used for 16
>> +bit multiply operations.
> 
> "16-bit", with a hyphen.
> 
>> +@item M
>> +The integer constant -1.
> 
> @minus{}1.
> 
>> +Integer constants -4 through -1 and 1 through 4; shifts by these
> 
> Likewise, @minus{}4 and @minus{1}.

Thanks!  Done.

	paul

ChangeLog:

2010-11-04  Paul Koning  <ni1d@arrl.net>

	* doc/md.texi (Machine Constraints): Correct formatting in PDP-11
	constraints.

Patch

Index: doc/md.texi
===================================================================
--- doc/md.texi	(revision 166335)
+++ doc/md.texi	(working copy)
@@ -2928,8 +2928,8 @@ 
 memory with a single instruction.
 
 @item d
-Odd numbered general registers (R1, R3, R5).  These are used for 16
-bit multiply operations.
+Odd numbered general registers (R1, R3, R5).  These are used for
+16-bit multiply operations.
 
 @item f
 Any of the floating point registers (AC0 through AC5).
@@ -2951,13 +2951,13 @@ 
 The integer constant 1.
 
 @item M
-The integer constant -1.
+The integer constant @minus{}1.
 
 @item N
 The integer constant 0.
 
 @item O
-Integer constants -4 through -1 and 1 through 4; shifts by these
+Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
 amounts are handled as multiple single-bit shifts rather than a single
 variable-length shift.