Message ID | a7809e0c-2506-ba08-53e1-4fef8a772c83@linux.vnet.ibm.com |
---|---|
State | New |
Headers | show |
On Wed, Nov 30, 2016 at 08:35:08AM -0700, Kelvin Nilsen wrote: > This patch corrects an error in a patch committed on 2016-10-18 to add > built-in function support for Power9 string operations. In that > original patch, the mode for operand 2 of the newly added vector > extract half-word and full-word instruction patterns was described as > V16QI, even though those instruction patterns were conceptually > operating on V8HI and V4SI operands respectively. > > This patch changes the modes of the operands for these instruction > patterns to better represent the intended types. This patch improves > readability and maintainability of code. It does not affect > correctness of generated code, since the existing implementation > implicitly coerces the operand types to the declared type. > > The patch has been bootstrapped and tested on powerpc64le-unknown-linux > without regressions. > > Is this ok for the trunk? Okay. Thanks, Segher > 2016-11-30 Kelvin Nilsen <kelvin@gcc.gnu.org> > > PR target/78577 > * config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2. > (vextuhrx): Likewise. > (vextuwlx): Likewise. > (vextuwrx): Likewise.
Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 242948) +++ gcc/config/rs6000/vsx.md (working copy) @@ -3648,7 +3648,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V8HI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUHLX))] "TARGET_P9_VECTOR" "vextuhlx %0,%1,%2" @@ -3659,7 +3659,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V8HI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUHRX))] "TARGET_P9_VECTOR" "vextuhrx %0,%1,%2" @@ -3670,7 +3670,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V4SI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUWLX))] "TARGET_P9_VECTOR" "vextuwlx %0,%1,%2" @@ -3681,7 +3681,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V4SI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUWRX))] "TARGET_P9_VECTOR" "vextuwrx %0,%1,%2"