From patchwork Wed Nov 3 17:46:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 70043 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id BBE96B70A9 for ; Thu, 4 Nov 2010 04:46:41 +1100 (EST) Received: (qmail 9110 invoked by alias); 3 Nov 2010 17:46:35 -0000 Received: (qmail 8895 invoked by uid 22791); 3 Nov 2010 17:46:31 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, TW_MF, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e8.ny.us.ibm.com (HELO e8.ny.us.ibm.com) (32.97.182.138) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 03 Nov 2010 17:46:26 +0000 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by e8.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id oA3HTk9Z029296 for ; Wed, 3 Nov 2010 13:29:46 -0400 Received: from d03av04.boulder.ibm.com (d03av04.boulder.ibm.com [9.17.195.170]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id oA3HkM75172396 for ; Wed, 3 Nov 2010 13:46:22 -0400 Received: from d03av04.boulder.ibm.com (loopback [127.0.0.1]) by d03av04.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id oA3HkLdS027024 for ; Wed, 3 Nov 2010 11:46:22 -0600 Received: from hungry-tiger.westford.ibm.com (dyn9033037049.westford.ibm.com [9.33.37.49]) by d03av04.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id oA3HkLBl026984; Wed, 3 Nov 2010 11:46:21 -0600 Received: by hungry-tiger.westford.ibm.com (Postfix, from userid 500) id D38D7F84CC; Wed, 3 Nov 2010 13:46:20 -0400 (EDT) Date: Wed, 3 Nov 2010 13:46:20 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH] Don't set -mfprnd on power5 Message-ID: <20101103174620.GA16777@hungry-tiger.westford.ibm.com> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Off the list, David asked me to check the floating point conversion patches for various machines to make sure we weren't generating instructions that aren't implemented for various -mcpu= targets. I discovered that -mcpu=power5 was generating the FRIZ instruciton (and other rounding instrucitons) that were added in ISA 2.04 (power5+). This wasn't in the fp conversion patches I just submitted, but in patches we submitted earlier. This patch restricts the (double)(long long) optimization to use FRIZ to machines with FPRND, and does not set the FPRND flag for -mcpu=power5. I have bootstraped the compiler with these tests, and done unit tests on a power5 machine to make sure the FRIZ instruction is not generated. My unit test of doing all possible conversions and rounds works fine on the power5 machine. Is this patch ok to apply? Note, the patch won't apply cleanly to the target attributes patch, since the enum got moved to file scope in that patch. 2010-11-03 Michael Meissner * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't turn on ISA 2.04 rounding instructions for power5. * config/rs6000/rs6000.md (friz): Friz is an ISA 2.04 instruciton, not ISA 2.02. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 166212) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -2569,7 +2569,8 @@ rs6000_option_override_internal (const c /* Masks for instructions set at various powerpc ISAs. */ enum { ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB | MASK_FPRND), + ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), + ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, @@ -2738,7 +2739,9 @@ rs6000_option_override_internal (const c target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); else if (TARGET_CMPB) target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); - else if (TARGET_POPCNTB || TARGET_FPRND) + else if (TARGET_FPRND) + target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + else if (TARGET_POPCNTB) target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); else if (TARGET_ALTIVEC) target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 166212) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -7142,7 +7142,7 @@ (define_insn "fctiwuz_" (define_insn "*friz" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_POPCNTB + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" "friz %0,%1"