From patchwork Tue Nov 2 09:32:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 69896 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 19C02B6F0D for ; Wed, 3 Nov 2010 02:28:14 +1100 (EST) Received: from localhost ([127.0.0.1]:36657 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PDImQ-00053P-AQ for incoming@patchwork.ozlabs.org; Tue, 02 Nov 2010 11:28:10 -0400 Received: from [140.186.70.92] (port=35968 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PDH6F-0004ML-JZ for qemu-devel@nongnu.org; Tue, 02 Nov 2010 09:40:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PDDEg-0001Cu-Si for qemu-devel@nongnu.org; Tue, 02 Nov 2010 05:33:00 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:40514) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PDDEg-0001Bq-C6 for qemu-devel@nongnu.org; Tue, 02 Nov 2010 05:32:58 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id EBA458743C; Tue, 2 Nov 2010 18:32:52 +0900 (JST) Received: (nullmailer pid 26003 invoked by uid 1000); Tue, 02 Nov 2010 09:32:52 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Tue, 2 Nov 2010 18:32:50 +0900 Message-Id: <6cfb368062b8cbef232c6981ae2cb7d1a5437002.1288689399.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v7 4/6] ioh3420: support aer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add aer support. Signed-off-by: Isaku Yamahata --- hw/ioh3420.c | 51 +++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 6 deletions(-) diff --git a/hw/ioh3420.c b/hw/ioh3420.c index 3cc129f..4eecf2f 100644 --- a/hw/ioh3420.c +++ b/hw/ioh3420.c @@ -36,25 +36,59 @@ #define IOH_EP_EXP_OFFSET 0x90 #define IOH_EP_AER_OFFSET 0x100 +/* + * If two MSI vector are allocated, Advanced Error Interrupt Message Number + * is 1. otherwise 0. + * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. + */ +static uint8_t ioh3420_aer_vector(const PCIDevice *d) +{ + switch (msi_nr_vectors_allocated(d)) { + case 1: + return 0; + case 2: + return 1; + case 4: + case 8: + case 16: + case 32: + default: + break; + } + abort(); + return 0; +} + +static void ioh3420_aer_vector_update(PCIDevice *d) +{ + pcie_aer_root_set_vector(d, ioh3420_aer_vector(d)); +} + static void ioh3420_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { + uint32_t root_cmd = + pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); + pci_bridge_write_config(d, address, val, len); msi_write_config(d, address, val, len); + ioh3420_aer_vector_update(d); pcie_cap_slot_write_config(d, address, val, len); - /* TODO: AER */ + pcie_aer_write_config(d, address, val, len); + pcie_aer_root_write_config(d, address, val, len, root_cmd); } static void ioh3420_reset(DeviceState *qdev) { PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); msi_reset(d); + ioh3420_aer_vector_update(d); pcie_cap_root_reset(d); pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); + pcie_aer_root_reset(d); pci_bridge_reset(qdev); pci_bridge_disable_base_limit(d); - /* TODO: AER */ } static int ioh3420_initfn(PCIDevice *d) @@ -98,13 +132,15 @@ static int ioh3420_initfn(PCIDevice *d) return rc; } pcie_cap_root_init(d); - /* TODO: AER */ + pcie_aer_init(d, IOH_EP_AER_OFFSET); + pcie_aer_root_init(d); + ioh3420_aer_vector_update(d); return 0; } static int ioh3420_exitfn(PCIDevice *d) { - /* TODO: AER */ + pcie_aer_exit(d); msi_uninit(d); pcie_cap_exit(d); return pci_bridge_exitfn(d); @@ -142,7 +178,8 @@ static const VMStateDescription vmstate_ioh3420 = { .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), - /* TODO: AER */ + VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, + vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } }; @@ -164,7 +201,9 @@ static PCIDeviceInfo ioh3420_info = { DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), - /* TODO: AER */ + DEFINE_PROP_UINT16("aer_log_max", PCIESlot, + port.br.dev.exp.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), } };