diff mbox

[U-Boot,48/97] powerpc: P1021: Remove macro CONFIG_P1021

Message ID 1479974118-2912-48-git-send-email-york.sun@nxp.com
State Accepted
Commit a990799d5248d3bb92bf2a8919936e1562693b07
Delegated to: York Sun
Headers show

Commit Message

York Sun Nov. 24, 2016, 7:54 a.m. UTC 
Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
---

 arch/powerpc/cpu/mpc85xx/Kconfig          |  4 ++++
 arch/powerpc/cpu/mpc85xx/Makefile         |  2 +-
 arch/powerpc/cpu/mpc85xx/speed.c          |  2 +-
 arch/powerpc/include/asm/config_mpc85xx.h |  2 +-
 arch/powerpc/include/asm/immap_85xx.h     |  2 +-
 drivers/qe/uec.c                          | 10 +++++-----
 include/configs/p1_p2_rdb_pc.h            |  1 -
 scripts/config_whitelist.txt              |  1 -
 8 files changed, 13 insertions(+), 11 deletions(-)
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9142b33..5550687 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -144,6 +144,7 @@  config TARGET_P1021RDB
 	bool "Support P1021RDB"
 	select SUPPORT_SPL
 	select SUPPORT_TPL
+	select ARCH_P1021
 
 config TARGET_P1024RDB
 	bool "Support P1024RDB"
@@ -287,6 +288,9 @@  config ARCH_P1011
 config ARCH_P1020
 	bool
 
+config ARCH_P1021
+	bool
+
 config ARCH_P1022
 	bool
 
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 26a6786..515647d 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -75,7 +75,7 @@  obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
 obj-$(CONFIG_ARCH_P1010)	+= p1010_serdes.o
 obj-$(CONFIG_ARCH_P1011)	+= p1021_serdes.o
 obj-$(CONFIG_ARCH_P1020)	+= p1021_serdes.o
-obj-$(CONFIG_P1021)	+= p1021_serdes.o
+obj-$(CONFIG_ARCH_P1021)	+= p1021_serdes.o
 obj-$(CONFIG_ARCH_P1022)	+= p1022_serdes.o
 obj-$(CONFIG_ARCH_P1023)	+= p1023_serdes.o
 obj-$(CONFIG_P1024)	+= p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 4e63859..8155620 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -596,7 +596,7 @@  void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_QE
-#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 	sys_info->freq_qe =  sys_info->freq_systembus;
 #else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4947e18..bcd7550 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -199,7 +199,7 @@ 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 
-#elif defined(CONFIG_P1021)
+#elif defined(CONFIG_ARCH_P1021)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c82c709..b0f81ec 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2488,7 +2488,7 @@  typedef struct ccsr_gur {
 	u8	res11a[76];
 	par_io_t qe_par_io[7];
 	u8	res11b[1600];
-#elif defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 	u8      res11a[12];
 	u32     iovselsr;
 	u8      res11b[60];
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index d0398d2..2bb630d 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -567,7 +567,7 @@  static void phy_change(struct eth_device *dev)
 {
 	uec_private_t	*uec = (uec_private_t *)dev->priv;
 
-#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
@@ -578,7 +578,7 @@  static void phy_change(struct eth_device *dev)
 	/* Update the link, speed, duplex */
 	uec->mii_info->phyinfo->read_status(uec->mii_info);
 
-#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 	/*
 	 * QE12 is muxed with LBCTL, it needs to be released for enabling
 	 * LBCTL signal for LBC usage.
@@ -1193,14 +1193,14 @@  static int uec_init(struct eth_device* dev, bd_t *bd)
 	uec_private_t		*uec;
 	int			err, i;
 	struct phy_info         *curphy;
-#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
 	uec = (uec_private_t *)dev->priv;
 
 	if (uec->the_first_run == 0) {
-#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@@ -1232,7 +1232,7 @@  static int uec_init(struct eth_device* dev, bd_t *bd)
 			udelay(100000);
 		} while (1);
 
-#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025)
 		/* QE12 needs to be released for enabling LBCTL signal*/
 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 #endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index c9191fa..5689113 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -82,7 +82,6 @@ 
 #if defined(CONFIG_TARGET_P1021RDB)
 #define CONFIG_BOARDNAME "P1021RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1021
 #define CONFIG_QE
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 858c2d0..9bee3fe 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3383,7 +3383,6 @@  CONFIG_OS2_ENV_ADDR
 CONFIG_OS_ENV_ADDR
 CONFIG_OTHBOOTARGS
 CONFIG_OVERWRITE_ETHADDR_ONCE
-CONFIG_P1021
 CONFIG_P1024
 CONFIG_P1025
 CONFIG_P2020