@@ -2767,6 +2767,11 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
.driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
.property = "mem64_win_size", \
.value = "0", \
+ }, \
+ { \
+ .driver = TYPE_POWERPC_CPU, \
+ .property = "pre-2.8-migration", \
+ .value = "on", \
},
static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
@@ -1167,7 +1167,8 @@ struct PowerPCCPU {
uint32_t max_compat;
uint32_t cpu_version;
- /* fields used only during migration for compatibility hacks */
+ /* Fields related to migration compatibility hacks */
+ bool pre_2_8_migration;
target_ulong mig_msr_mask;
uint64_t mig_insns_flags;
uint64_t mig_insns_flags2;
@@ -135,6 +135,13 @@ static const VMStateInfo vmstate_info_avr = {
#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
+static bool cpu_pre_2_8_migration(void *opaque, int version_id)
+{
+ PowerPCCPU *cpu = opaque;
+
+ return cpu->pre_2_8_migration;
+}
+
static void cpu_pre_save(void *opaque)
{
PowerPCCPU *cpu = opaque;
@@ -179,10 +186,12 @@ static void cpu_pre_save(void *opaque)
}
/* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
- cpu->mig_msr_mask = env->msr_mask;
- cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
- cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
- cpu->mig_nb_BATs = env->nb_BATs;
+ if (cpu->pre_2_8_migration) {
+ cpu->mig_msr_mask = env->msr_mask;
+ cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
+ cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
+ cpu->mig_nb_BATs = env->nb_BATs;
+ }
}
static int cpu_post_load(void *opaque, int version_id)
@@ -230,15 +239,19 @@ static int cpu_post_load(void *opaque, int version_id)
hreg_compute_mem_idx(env);
- if (cpu->mig_insns_flags != env->insns_flags) {
- fprintf(stderr, "INSNS: Added 0x%" PRIx64 " removed 0x%" PRIx64 "\n",
- env->insns_flags & ~cpu->mig_insns_flags,
- cpu->mig_insns_flags & ~env->insns_flags);
- }
- if (cpu->mig_insns_flags2 != env->insns_flags2) {
- fprintf(stderr, "INSNS2: Added 0x%" PRIx64 " removed 0x%" PRIx64 "\n",
- env->insns_flags2 & ~cpu->mig_insns_flags2,
- cpu->mig_insns_flags2 & ~env->insns_flags2);
+ if (cpu->pre_2_8_migration) {
+ if (cpu->mig_insns_flags != env->insns_flags) {
+ fprintf(stderr,
+ "INSNS: Added 0x%" PRIx64 " removed 0x%" PRIx64 "\n",
+ env->insns_flags & ~cpu->mig_insns_flags,
+ cpu->mig_insns_flags & ~env->insns_flags);
+ }
+ if (cpu->mig_insns_flags2 != env->insns_flags2) {
+ fprintf(stderr,
+ "INSNS2: Added 0x%" PRIx64 " removed 0x%" PRIx64 "\n",
+ env->insns_flags2 & ~cpu->mig_insns_flags2,
+ cpu->mig_insns_flags2 & ~env->insns_flags2);
+ }
}
return 0;
@@ -594,10 +607,11 @@ const VMStateDescription vmstate_ppc_cpu = {
/* FIXME: access_type? */
/* Sanity checking */
- VMSTATE_UINTTL(mig_msr_mask, PowerPCCPU),
- VMSTATE_UINT64(mig_insns_flags, PowerPCCPU),
- VMSTATE_UINT64(mig_insns_flags2, PowerPCCPU),
- VMSTATE_UINT32(mig_nb_BATs, PowerPCCPU),
+ VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
+ VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
+ VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
+ cpu_pre_2_8_migration),
+ VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
@@ -10520,6 +10520,11 @@ static gchar *ppc_gdb_arch_name(CPUState *cs)
#endif
}
+static Property ppc_cpu_properties[] = {
+ DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void ppc_cpu_class_init(ObjectClass *oc, void *data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
@@ -10532,6 +10537,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
dc->realize = ppc_cpu_realizefn;
dc->unrealize = ppc_cpu_unrealizefn;
+ dc->props = ppc_cpu_properties;
pcc->parent_reset = cc->reset;
cc->reset = ppc_cpu_reset;