diff mbox

[U-Boot,v2,60/63] x86: link: Set up device tree for SPL

Message ID 1479587152-25065-61-git-send-email-sjg@chromium.org
State Superseded
Delegated to: Bin Meng
Headers show

Commit Message

Simon Glass Nov. 19, 2016, 8:25 p.m. UTC 
Add the correct pre-relocation tag so that the required device tree nodes
are present in the SPL device tree.

On x86 it doesn't make a lot of sense to have a separate SPL device tree.
Since everything is in the same ROM we might as well just use the main
device tree in both SPL and U-Boot proper. But we haven't implemented that,
so this is a good first step.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Bin Meng Jan. 14, 2017, 1:33 p.m. UTC | #1 
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass <sjg@chromium.org> wrote:
> Add the correct pre-relocation tag so that the required device tree nodes
> are present in the SPL device tree.
>
> On x86 it doesn't make a lot of sense to have a separate SPL device tree.
> Since everything is in the same ROM we might as well just use the main
> device tree in both SPL and U-Boot proper. But we haven't implemented that,
> so this is a good first step.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox

Patch

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index b932340..fab919a 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -26,12 +26,14 @@ 
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
 
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "intel,core-gen3";
 			reg = <0>;
 			intel,apic-id = <0>;
+			u-boot,dm-pre-reloc;
 		};
 
 		cpu@1 {
@@ -39,6 +41,7 @@ 
 			compatible = "intel,core-gen3";
 			reg = <1>;
 			intel,apic-id = <1>;
+			u-boot,dm-pre-reloc;
 		};
 
 		cpu@2 {
@@ -46,6 +49,7 @@ 
 			compatible = "intel,core-gen3";
 			reg = <2>;
 			intel,apic-id = <2>;
+			u-boot,dm-pre-reloc;
 		};
 
 		cpu@3 {
@@ -53,6 +57,7 @@ 
 			compatible = "intel,core-gen3";
 			reg = <3>;
 			intel,apic-id = <3>;
+			u-boot,dm-pre-reloc;
 		};
 
 	};
@@ -229,14 +234,16 @@ 
 
 		northbridge@0,0 {
 			reg = <0x00000000 0 0 0 0>;
+			u-boot,dm-pre-reloc;
 			compatible = "intel,bd82x6x-northbridge";
 			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
 					<&gpio_b 11 0>, <&gpio_a 10 0>;
-			u-boot,dm-pre-reloc;
 			spd {
+				u-boot,dm-pre-reloc;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				elpida_4Gb_1600_x16 {
+					u-boot,dm-pre-reloc;
 					reg = <0>;
 					data = [92 10 0b 03 04 19 02 02
 						03 52 01 08 0a 00 fe 00
@@ -272,6 +279,7 @@ 
 						00 00 00 00 00 00 00 00];
 				};
 				samsung_4Gb_1600_1.35v_x16 {
+					u-boot,dm-pre-reloc;
 					reg = <1>;
 					data = [92 11 0b 03 04 19 02 02
 						03 11 01 08 0a 00 fe 00
@@ -391,9 +399,11 @@ 
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
+				u-boot,dm-pre-reloc;
 				spi-flash@0 {
 					#size-cells = <1>;
 					#address-cells = <1>;
+					u-boot,dm-pre-reloc;
 					reg = <0>;
 					compatible = "winbond,w25q64",
 							"spi-flash";
@@ -401,6 +411,7 @@ 
 					rw-mrc-cache {
 						label = "rw-mrc-cache";
 						reg = <0x003e0000 0x00010000>;
+						u-boot,dm-pre-reloc;
 					};
 				};
 			};
@@ -478,7 +489,9 @@ 
 	};
 
 	microcode {
+		u-boot,dm-pre-reloc;
 		update@0 {
+			u-boot,dm-pre-reloc;
 #include "microcode/m12306a9_0000001b.dtsi"
 		};
 	};