| Message ID | 1479445519-23865-4-git-send-email-gwshan@linux.vnet.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
On Fri, 2016-11-18 at 16:05 +1100, Gavin Shan wrote: > The PCI config register is applied before the HW register is changed. > It won't work when this mechanism is used to capture the change to > SRIOV capability in subsequent patch. > > This moves the logic around so that the filter is applied after HW > register is changed. Currently, it's used to cache bridge's pref > window base/length. The code change shouldn't affect that. So no > functional changes introduced by this. > > Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> > --- Reviewed-by: Russell Currey <ruscur@russell.cc>
diff --git a/hw/phb3.c b/hw/phb3.c index d6ff033..8a93aa9 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -232,9 +232,6 @@ static int64_t phb3_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \ return OPAL_HARDWARE; \ } \ \ - phb3_pcicfg_filter(phb, bdfn, offset, sizeof(type), \ - (uint32_t *)&data, true); \ - \ addr = PHB_CA_ENABLE; \ addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \ addr = SETFIELD(PHB_CA_REG, addr, offset); \ @@ -251,6 +248,9 @@ static int64_t phb3_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \ (offset & (4 - sizeof(type))), data); \ } \ \ + phb3_pcicfg_filter(phb, bdfn, offset, sizeof(type), \ + (uint32_t *)&data, true); \ + \ return OPAL_SUCCESS; \ }
The PCI config register is applied before the HW register is changed. It won't work when this mechanism is used to capture the change to SRIOV capability in subsequent patch. This moves the logic around so that the filter is applied after HW register is changed. Currently, it's used to cache bridge's pref window base/length. The code change shouldn't affect that. So no functional changes introduced by this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> --- hw/phb3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)