diff mbox

[v3] powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1

Message ID 20161118030856.12445-1-mikey@neuling.org (mailing list archive)
State Accepted
Headers show

Commit Message

Michael Neuling Nov. 18, 2016, 3:08 a.m. UTC 
On POWER9 DD1, when we do a local TLB invalidate we also need to explicitly
invalidate the ERAT.

Signed-off-by: Michael Neuling <mikey@neuling.org>
---
v3:
  - Now with added bike shedding
v2:
  - Remove unnecessary isyncs
---
 arch/powerpc/include/asm/ppc-opcode.h | 1 +
 arch/powerpc/mm/tlb-radix.c           | 4 ++++
 2 files changed, 5 insertions(+)

Comments

Michael Ellerman Nov. 22, 2016, 12:38 a.m. UTC | #1 
On Fri, 2016-11-18 at 03:08:56 UTC, Michael Neuling wrote:
> On POWER9 DD1, when we do a local TLB invalidate we also need to explicitly
> invalidate the ERAT.
> 
> Signed-off-by: Michael Neuling <mikey@neuling.org>

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/96ed1fe511a8b4948e53f3bad431d8

cheers
diff mbox

Patch

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 0132831b30..c56ea8c84a 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -460,5 +460,6 @@ 
 
 #define PPC_SLBIA(IH)	stringify_in_c(.long PPC_INST_SLBIA | \
 				       ((IH & 0x7) << 21))
+#define PPC_INVALIDATE_ERAT	PPC_SLBIA(7)
 
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index bda8c43be7..3493cf4e04 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -50,6 +50,8 @@  static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
 	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
 		__tlbiel_pid(pid, set, ric);
 	}
+	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 	return;
 }
 
@@ -83,6 +85,8 @@  static inline void _tlbiel_va(unsigned long va, unsigned long pid,
 	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
 		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 	asm volatile("ptesync": : :"memory");
+	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 }
 
 static inline void _tlbie_va(unsigned long va, unsigned long pid,