From patchwork Fri Oct 29 19:48:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Koning X-Patchwork-Id: 69628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 1F2B7B70E0 for ; Sat, 30 Oct 2010 06:48:44 +1100 (EST) Received: (qmail 19711 invoked by alias); 29 Oct 2010 19:48:42 -0000 Received: (qmail 19701 invoked by uid 22791); 29 Oct 2010 19:48:41 -0000 X-SWARE-Spam-Status: No, hits=-0.8 required=5.0 tests=AWL, BAYES_20, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from ausc60ps301.us.dell.com (HELO ausc60ps301.us.dell.com) (143.166.148.206) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 29 Oct 2010 19:48:35 +0000 X-Loopcount0: from 10.152.240.141 From: Paul Koning Subject: [PATCH] PR/41822 pdp11: fix wrong code for and operation Date: Fri, 29 Oct 2010 15:48:32 -0400 Message-Id: <68AF8014-024B-4FB6-B341-703AB7B17FB4@dell.com> To: gcc-patches Mime-Version: 1.0 (Apple Message framework v1081) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org PDP11 has a bic instruction, which is and not. The code generation for that was wrong. Fixed by borrowing, with changes, from vax.md. Tested by test build, inspection of generated assembly code. Committed. ChangeLog: 2010-10-29 Paul Koning PR/41822 * config/pdp11/pdp11.md (andhi3, andqi3): Fix wrong code error. Index: config/pdp11/pdp11.md =================================================================== --- config/pdp11/pdp11.md (revision 166060) +++ config/pdp11/pdp11.md (working copy) @@ -43,6 +43,11 @@ ;; HI is 16 bit ;; QI is 8 bit +;; Integer modes supported on the PDP11, with a mapping from machine mode +;; to mnemonic suffix. SImode and DImode always are special cases. +(define_mode_iterator PDPint [QI HI]) +(define_mode_attr isfx [(QI "b") (HI "")]) + ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code @@ -809,71 +814,41 @@ ;;;;- and instructions ;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn. -(define_insn "andsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") - (and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") - (not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))] +(define_expand "and3" + [(set (match_operand:PDPint 0 "general_operand" "") + (and:PDPint (not:PDPint (match_operand:PDPint 1 "general_operand" "")) + (match_operand:PDPint 2 "general_operand" "")))] "" - "* -{ /* Here we trust that operands don't overlap + " +{ + rtx op1 = operands[1]; - or is lateoperands the low word?? - looks like it! */ + /* If there is a constant argument, complement that one. + Similarly, if one of the inputs is the same as the output, + complement the other input. */ + if ((CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) || + rtx_equal_p (operands[0], operands[1])) + { + operands[1] = operands[2]; + operands[2] = op1; + op1 = operands[1]; + } - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; - - if (REG_P (operands[0])) - operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + if (CONST_INT_P (op1)) + operands[1] = GEN_INT (~INTVAL (op1)); else - operands[0] = adjust_address (operands[0], HImode, 2); - - if (! CONSTANT_P(operands[2])) - { - lateoperands[2] = operands[2]; + operands[1] = expand_unop (mode, one_cmpl_optab, op1, 0, 1); +}") - if (REG_P (operands[2])) - operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1); - else - operands[2] = adjust_address (operands[2], HImode, 2); - - output_asm_insn (\"bic %2, %0\", operands); - output_asm_insn (\"bic %2, %0\", lateoperands); - return \"\"; - } - - lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff); - operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); - - /* these have different lengths, so we should have - different constraints! */ - if (INTVAL(operands[2])) - output_asm_insn (\"bic %2, %0\", operands); - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"bic %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "4,8,8,12,4,4,8,6,6,12")]) - -;; FIXME This definition is wrong, PR/41822 -(define_insn "andhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (and:HI (match_operand:HI 1 "general_operand" "0,0,0,0") - (not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))] +(define_insn "*and" + [(set (match_operand:PDPint 0 "general_operand" "=rR,rR,Q,Q") + (and:PDPint + (not: PDPint (match_operand:PDPint 1 "general_operand" "rR,Qi,rR,Qi")) + (match_operand:PDPint 2 "general_operand" "0,0,0,0")))] "" - "bic %2, %0" + "bic %1, %0" [(set_attr "length" "2,4,4,6")]) -(define_insn "andqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (and:QI (match_operand:QI 1 "general_operand" "0,0,0,0") - (not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))] - "" - "bicb %2, %0" - [(set_attr "length" "2,4,4,6")]) - ;;- Bit set (inclusive or) instructions (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")