Patchwork [rx] add register-specific constraints

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Submitter DJ Delorie
Date Oct. 29, 2010, 5:58 a.m.
Message ID <201010290558.o9T5whGR027913@greed.delorie.com>
Download mbox | patch
Permalink /patch/69556/
State New
Headers show

Comments

DJ Delorie - Oct. 29, 2010, 5:58 a.m.
Some of the RX opcodes use specific registers, despite gcc's usual
patterns not needing them.  This adds constraints for those registers
only so that source-level asm()s can refer to them.  Ok?

	* config/rx/rx.h (R1_REGS, R2_REGS, R3_REGS, R4_REGS, R5_REGS,
	R45_REGS, R6_REGS): Add new register-specific classes.
	* config/rx/constraints: Add constaints for them.
Richard Henderson - Oct. 31, 2010, 12:33 a.m.
On 10/28/2010 10:58 PM, DJ Delorie wrote:
> Some of the RX opcodes use specific registers, despite gcc's usual
> patterns not needing them.  This adds constraints for those registers
> only so that source-level asm()s can refer to them.  Ok?
> 
> 	* config/rx/rx.h (R1_REGS, R2_REGS, R3_REGS, R4_REGS, R5_REGS,
> 	R45_REGS, R6_REGS): Add new register-specific classes.
> 	* config/rx/constraints: Add constaints for them.

Source-level asms can use registers.  E.g.

  register int r1 __asm__("r1");
  asm ("" : "=r"(r1));

That's guaranteed to not replace the hard register in the asm.
Glibc and the linux kernel relies on this for a number of ports,
so it's unlikely to ever break.

Is there any other reason to add these?


r~
DJ Delorie - Nov. 1, 2010, 6:13 p.m.
> Source-level asms can use registers.  E.g.
> 
>   register int r1 __asm__("r1");
>   asm ("" : "=r"(r1));
> 
> That's guaranteed to not replace the hard register in the asm.
> Glibc and the linux kernel relies on this for a number of ports,
> so it's unlikely to ever break.
> 
> Is there any other reason to add these?

Does that work for register pairs?
Richard Henderson - Nov. 1, 2010, 6:22 p.m.
On 11/01/2010 11:13 AM, DJ Delorie wrote:
>> Source-level asms can use registers.  E.g.
>>
>>   register int r1 __asm__("r1");
>>   asm ("" : "=r"(r1));
>>
>> That's guaranteed to not replace the hard register in the asm.
>> Glibc and the linux kernel relies on this for a number of ports,
>> so it's unlikely to ever break.
>>
>> Is there any other reason to add these?
> 
> Does that work for register pairs?

Sure.


r~
DJ Delorie - Nov. 1, 2010, 6:42 p.m.
> >> Source-level asms can use registers.  E.g.
> >>
> >>   register int r1 __asm__("r1");
> >>   asm ("" : "=r"(r1));
> >>
> >> That's guaranteed to not replace the hard register in the asm.
> >> Glibc and the linux kernel relies on this for a number of ports,
> >> so it's unlikely to ever break.
> >>
> >> Is there any other reason to add these?
> > 
> > Does that work for register pairs?
> 
> Sure.

Seems to work.  I withdraw that patch then (for now :).

Patch

Index: constraints.md
===================================================================
--- constraints.md	(revision 166029)
+++ constraints.md	(working copy)
@@ -83,6 +83,34 @@ 
 		      (match_code "const_int" "01")
 		 )
 	    )
        )
   )
 )
+
+(define_register_constraint "R01"
+  "R1_REGS"
+  "Register R1")
+
+(define_register_constraint "R02"
+  "R2_REGS"
+  "Register R2")
+
+(define_register_constraint "R03"
+  "R3_REGS"
+  "Register R3")
+
+(define_register_constraint "R04"
+  "R4_REGS"
+  "Register R4")
+
+(define_register_constraint "R05"
+  "R5_REGS"
+  "Register R5")
+
+(define_register_constraint "R45"
+  "R45_REGS"
+  "Register R5:R4")
+
+(define_register_constraint "R06"
+  "R6_REGS"
+  "Register R6")
Index: rx.h
===================================================================
--- rx.h	(revision 166029)
+++ rx.h	(working copy)
@@ -162,27 +162,48 @@  extern enum rx_cpu_types  rx_cpu_type;
 #define LOAD_EXTEND_OP(MODE)		SIGN_EXTEND
 #define SHORT_IMMEDIATES_SIGN_EXTEND	1
 
 enum reg_class
 {
   NO_REGS,			/* No registers in set.  */
+  R1_REGS,
+  R2_REGS,
+  R3_REGS,
+  R4_REGS,
+  R5_REGS,
+  R45_REGS,
+  R6_REGS,
   GR_REGS,			/* Integer registers.  */
   ALL_REGS,			/* All registers.  */
   LIM_REG_CLASSES		/* Max value + 1.  */
 };
 
 #define REG_CLASS_NAMES					\
 {							\
   "NO_REGS",						\
+  "R1_REGS",						\
+  "R2_REGS",						\
+  "R3_REGS",						\
+  "R4_REGS",						\
+  "R5_REGS",						\
+  "R54_REGS",						\
+  "R6_REGS",						\
   "GR_REGS",						\
   "ALL_REGS"						\
 }
 
 #define REG_CLASS_CONTENTS				\
 {							\
   { 0x00000000 },	/* No registers,  */		\
+  { 0x00000002 },					\
+  { 0x00000004 },					\
+  { 0x00000008 },					\
+  { 0x00000010 },					\
+  { 0x00000020 },					\
+  { 0x00000030 },					\
+  { 0x00000040 },					\
   { 0x0000ffff },	/* Integer registers.  */	\
   { 0x0000ffff }	/* All registers.  */		\
 }
 
 #define IRA_COVER_CLASSES				\
   {							\