Patchwork Remove enum reg_class from rtl.h

login
register
mail settings
Submitter Anatoly Sokolov
Date Oct. 27, 2010, 8:53 p.m.
Message ID <1694217376.20101028005328@post.ru>
Download mbox | patch
Permalink /patch/69411/
State New
Headers show

Comments

Anatoly Sokolov - Oct. 27, 2010, 8:53 p.m.
Hello.

  This patch change enum reg_class to reg_class_t type in function 
declaration in rtl.h. This should allow reduce dependency middle end *.c 
files from tm.h, when tm.h need to supply enum reg_class type for rtl.h only 
(for example c-parser.c).

  The patch has been bootstrapped on and regression tested on
x86_64-unknown-linux-gnu for c.

  OK to install?

        * reginfo.c (setup_reg_classes, invalid_mode_change_p): Change
        arguments type from enum reg_class to reg_class_t.
        (reg_preferred_class, reg_alternate_class, reg_cover_class): Change
        result type from enum reg_class to reg_class_t.
        (struct reg_pref): Change prefclass, altclass and coverclass records
        type from char to reg_class_t.
        * rtl.h (reg_preferred_class, reg_alternate_class, reg_cover_class,
        setup_reg_classes, invalid_mode_change_p): Update prototype.
        * cfg.c (dump_reg_info): Change rclass and altclass variables type
        from enum reg_class to reg_class_t.
        * ira-build.c (update_conflict_hard_reg_costs): Change cover_class
        and pref variables type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Change cover_class
        argument type from enum reg_class to reg_class_t.
        * ira-int.h (ira_allocate_and_set_costs): Change cover_class argument
        type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Update prototupe.
        * ira-costs.c (find_costs_and_classes): Cast value returned by
        reg_preferred_class to enum reg_class. Change rclass variable type
        from int to reg_class_t.
        (print_allocno_costs, print_pseudo_costs): Change rclass variable
        type from int to reg_class_t.
        * ira.c (ira_bad_reload_regno_1): Use REG_P and HARD_REGISTER_NUM_P
        predicates. Change pref variable type from enum reg_class to
        reg_class_t.
        * regmove.c (regmove_backward_pass): Change src_class and dst_class
        variables type from enum reg_class to reg_class_t.
        * reload.c (find_reloads): Change preferred_class array and tclass
        variable type from enum reg_class to reg_class_t.
        * haifa-sched.c (sched_regno_cover_class): Change type to
        reg_class_t *.
        (mark_regno_birth_or_death): Change cover_class variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (setup_insn_reg_pressure_info): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (sched_init): Change sched_regno_cover_class type to reg_class_t.
        Use HARD_REGISTER_NUM_P predicate.
        * sched-int.h (sched_regno_cover_class): Change type to
        reg_class_t *.
        * sched-deps.c (mark_insn_pseudo_birth, mark_insn_hard_regno_birth,
        mark_pseudo_death, mark_hard_regno_death): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        * loop-invariant.c (get_inv_cost, change_pressure,
        calculate_loop_reg_pressure): Change cover_class variable type
        from enum reg_class to reg_class_t.
        (get_cover_class_and_nregs, get_regno_cover_class): Change result and
        cover_class variable types from enum reg_class to reg_class_t.



Anatoly.
Anatoly Sokolov - Nov. 1, 2010, 8:11 p.m.
Hello.

>   This patch change enum reg_class to reg_class_t type in function 
> declaration in rtl.h. This should allow reduce dependency middle end *.c 
> files from tm.h, when tm.h need to supply enum reg_class type for rtl.h only 
> (for example c-parser.c).

http://gcc.gnu.org/ml/gcc-patches/2010-10/msg02374.html

        * reginfo.c (setup_reg_classes, invalid_mode_change_p): Change
        arguments type from enum reg_class to reg_class_t.
        (reg_preferred_class, reg_alternate_class, reg_cover_class): Change
        result type from enum reg_class to reg_class_t.
        (struct reg_pref): Change prefclass, altclass and coverclass records
        type from char to reg_class_t.
        * rtl.h (reg_preferred_class, reg_alternate_class, reg_cover_class,
        setup_reg_classes, invalid_mode_change_p): Update prototype.
        * cfg.c (dump_reg_info): Change rclass and altclass variables type
        from enum reg_class to reg_class_t.
        * ira-build.c (update_conflict_hard_reg_costs): Change cover_class
        and pref variables type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Change cover_class
        argument type from enum reg_class to reg_class_t.
        * ira-int.h (ira_allocate_and_set_costs): Change cover_class argument
        type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Update prototupe.
        * ira-costs.c (find_costs_and_classes): Cast value returned by
        reg_preferred_class to enum reg_class. Change rclass variable type
        from int to reg_class_t.
        (print_allocno_costs, print_pseudo_costs): Change rclass variable
        type from int to reg_class_t.
        * ira.c (ira_bad_reload_regno_1): Use REG_P and HARD_REGISTER_NUM_P
        predicates. Change pref variable type from enum reg_class to
        reg_class_t.
        * regmove.c (regmove_backward_pass): Change src_class and dst_class
        variables type from enum reg_class to reg_class_t.
        * reload.c (find_reloads): Change preferred_class array and tclass
        variable type from enum reg_class to reg_class_t.
        * haifa-sched.c (sched_regno_cover_class): Change type to
        reg_class_t *.
        (mark_regno_birth_or_death): Change cover_class variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (setup_insn_reg_pressure_info): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (sched_init): Change sched_regno_cover_class type to reg_class_t.
        Use HARD_REGISTER_NUM_P predicate.
        * sched-int.h (sched_regno_cover_class): Change type to
        reg_class_t *.
        * sched-deps.c (mark_insn_pseudo_birth, mark_insn_hard_regno_birth,
        mark_pseudo_death, mark_hard_regno_death): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        * loop-invariant.c (get_inv_cost, change_pressure,
        calculate_loop_reg_pressure): Change cover_class variable type
        from enum reg_class to reg_class_t.
        (get_cover_class_and_nregs, get_regno_cover_class): Change result and
        cover_class variable types from enum reg_class to reg_class_t.


Anatoly.
Anatoly Sokolov - Nov. 6, 2010, 8:01 p.m.
Hello.

>   This patch change enum reg_class to reg_class_t type in function 
> declaration in rtl.h. This should allow reduce dependency middle end *.c 
> files from tm.h, when tm.h need to supply enum reg_class type for rtl.h only 
> (for example c-parser.c).

http://gcc.gnu.org/ml/gcc-patches/2010-10/msg02374.html

        * reginfo.c (setup_reg_classes, invalid_mode_change_p): Change
        arguments type from enum reg_class to reg_class_t.
        (reg_preferred_class, reg_alternate_class, reg_cover_class): Change
        result type from enum reg_class to reg_class_t.
        (struct reg_pref): Change prefclass, altclass and coverclass records
        type from char to reg_class_t.
        * rtl.h (reg_preferred_class, reg_alternate_class, reg_cover_class,
        setup_reg_classes, invalid_mode_change_p): Update prototype.
        * cfg.c (dump_reg_info): Change rclass and altclass variables type
        from enum reg_class to reg_class_t.
        * ira-build.c (update_conflict_hard_reg_costs): Change cover_class
        and pref variables type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Change cover_class
        argument type from enum reg_class to reg_class_t.
        * ira-int.h (ira_allocate_and_set_costs): Change cover_class argument
        type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Update prototupe.
        * ira-costs.c (find_costs_and_classes): Cast value returned by
        reg_preferred_class to enum reg_class. Change rclass variable type
        from int to reg_class_t.
        (print_allocno_costs, print_pseudo_costs): Change rclass variable
        type from int to reg_class_t.
        * ira.c (ira_bad_reload_regno_1): Use REG_P and HARD_REGISTER_NUM_P
        predicates. Change pref variable type from enum reg_class to
        reg_class_t.
        * regmove.c (regmove_backward_pass): Change src_class and dst_class
        variables type from enum reg_class to reg_class_t.
        * reload.c (find_reloads): Change preferred_class array and tclass
        variable type from enum reg_class to reg_class_t.
        * haifa-sched.c (sched_regno_cover_class): Change type to
        reg_class_t *.
        (mark_regno_birth_or_death): Change cover_class variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (setup_insn_reg_pressure_info): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (sched_init): Change sched_regno_cover_class type to reg_class_t.
        Use HARD_REGISTER_NUM_P predicate.
        * sched-int.h (sched_regno_cover_class): Change type to
        reg_class_t *.
        * sched-deps.c (mark_insn_pseudo_birth, mark_insn_hard_regno_birth,
        mark_pseudo_death, mark_hard_regno_death): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        * loop-invariant.c (get_inv_cost, change_pressure,
        calculate_loop_reg_pressure): Change cover_class variable type
        from enum reg_class to reg_class_t.
        (get_cover_class_and_nregs, get_regno_cover_class): Change result and
        cover_class variable types from enum reg_class to reg_class_t.


Anatoly.
Anatoly Sokolov - Nov. 16, 2010, 3:20 p.m.
Hello.

>   This patch change enum reg_class to reg_class_t type in function 
> declaration in rtl.h. This should allow reduce dependency middle end *.c 
> files from tm.h, when tm.h need to supply enum reg_class type for rtl.h only 
> (for example c-parser.c).

http://gcc.gnu.org/ml/gcc-patches/2010-10/msg02374.html

        * reginfo.c (setup_reg_classes, invalid_mode_change_p): Change
        arguments type from enum reg_class to reg_class_t.
        (reg_preferred_class, reg_alternate_class, reg_cover_class): Change
        result type from enum reg_class to reg_class_t.
        (struct reg_pref): Change prefclass, altclass and coverclass records
        type from char to reg_class_t.
        * rtl.h (reg_preferred_class, reg_alternate_class, reg_cover_class,
        setup_reg_classes, invalid_mode_change_p): Update prototype.
        * cfg.c (dump_reg_info): Change rclass and altclass variables type
        from enum reg_class to reg_class_t.
        * ira-build.c (update_conflict_hard_reg_costs): Change cover_class
        and pref variables type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Change cover_class
        argument type from enum reg_class to reg_class_t.
        * ira-int.h (ira_allocate_and_set_costs): Change cover_class argument
        type from enum reg_class to reg_class_t.
        (ira_allocate_cost_vector, ira_free_cost_vector): Update prototupe.
        * ira-costs.c (find_costs_and_classes): Cast value returned by
        reg_preferred_class to enum reg_class. Change rclass variable type
        from int to reg_class_t.
        (print_allocno_costs, print_pseudo_costs): Change rclass variable
        type from int to reg_class_t.
        * ira.c (ira_bad_reload_regno_1): Use REG_P and HARD_REGISTER_NUM_P
        predicates. Change pref variable type from enum reg_class to
        reg_class_t.
        * regmove.c (regmove_backward_pass): Change src_class and dst_class
        variables type from enum reg_class to reg_class_t.
        * reload.c (find_reloads): Change preferred_class array and tclass
        variable type from enum reg_class to reg_class_t.
        * haifa-sched.c (sched_regno_cover_class): Change type to
        reg_class_t *.
        (mark_regno_birth_or_death): Change cover_class variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (setup_insn_reg_pressure_info): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        (sched_init): Change sched_regno_cover_class type to reg_class_t.
        Use HARD_REGISTER_NUM_P predicate.
        * sched-int.h (sched_regno_cover_class): Change type to
        reg_class_t *.
        * sched-deps.c (mark_insn_pseudo_birth, mark_insn_hard_regno_birth,
        mark_pseudo_death, mark_hard_regno_death): Change cl variable type
        from enum reg_class to reg_class_t. Use HARD_REGISTER_NUM_P
        predicate.
        * loop-invariant.c (get_inv_cost, change_pressure,
        calculate_loop_reg_pressure): Change cover_class variable type
        from enum reg_class to reg_class_t.
        (get_cover_class_and_nregs, get_regno_cover_class): Change result and
        cover_class variable types from enum reg_class to reg_class_t.


Anatoly.

Patch

Index: gcc/reload.c
===================================================================
--- gcc/reload.c        (revision 166014)
+++ gcc/reload.c        (working copy)
@@ -2571,7 +2571,7 @@ 
   const char *constraints[MAX_RECOG_OPERANDS];
   /* These are the preferred classes for an operand, or NO_REGS if it isn't
      a register.  */
-  enum reg_class preferred_class[MAX_RECOG_OPERANDS];
+  reg_class_t preferred_class[MAX_RECOG_OPERANDS];
   char pref_or_nothing[MAX_RECOG_OPERANDS];
   /* Nonzero for a MEM operand whose entire address needs a reload.
      May be -1 to indicate the entire address may or may not need a reload.  */
@@ -3752,7 +3752,7 @@ 
       swapped = !swapped;
       if (swapped)
        {
-         enum reg_class tclass;
+         reg_class_t tclass;
          int t;
 
          recog_data.operand[commutative] = substed_operand[commutative + 1];
Index: gcc/cfg.c
===================================================================
--- gcc/cfg.c   (revision 166014)
+++ gcc/cfg.c   (working copy)
@@ -598,7 +598,7 @@ 
   fprintf (file, "%d registers.\n", max);
   for (i = FIRST_PSEUDO_REGISTER; i < max; i++)
     {
-      enum reg_class rclass, altclass;
+      reg_class_t rclass, altclass;
 
       if (regstat_n_sets_and_refs)
        fprintf (file, "\nRegister %d used %d times across %d insns",
Index: gcc/haifa-sched.c
===================================================================
--- gcc/haifa-sched.c   (revision 166014)
+++ gcc/haifa-sched.c   (working copy)
@@ -591,7 +591,7 @@ 
 
 /* Map regno -> its cover class.  The map defined only when
    SCHED_PRESSURE_P is true.  */
-enum reg_class *sched_regno_cover_class;
+reg_class_t *sched_regno_cover_class;
 
 /* The current register pressure.  Only elements corresponding cover
    classes are defined.  */
@@ -623,24 +623,26 @@ 
 static void
 mark_regno_birth_or_death (int regno, bool birth_p)
 {
-  enum reg_class cover_class;
+  reg_class_t cover_class;
 
   cover_class = sched_regno_cover_class[regno];
-  if (regno >= FIRST_PSEUDO_REGISTER)
+  if (!HARD_REGISTER_NUM_P (regno))
     {
       if (cover_class != NO_REGS)
        {
          if (birth_p)
            {
              bitmap_set_bit (curr_reg_live, regno);
-             curr_reg_pressure[cover_class]
-               += ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
+             curr_reg_pressure[(int) cover_class]
+               += ira_reg_class_nregs
+                  [(int) cover_class][PSEUDO_REGNO_MODE (regno)];
            }
          else
            {
              bitmap_clear_bit (curr_reg_live, regno);
-             curr_reg_pressure[cover_class]
-               -= ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
+             curr_reg_pressure[(int) cover_class]
+               -= ira_reg_class_nregs
+                  [(int) cover_class][PSEUDO_REGNO_MODE (regno)];
            }
        }
     }
@@ -650,12 +652,12 @@ 
       if (birth_p)
        {
          bitmap_set_bit (curr_reg_live, regno);
-         curr_reg_pressure[cover_class]++;
+         curr_reg_pressure[(int) cover_class]++;
        }
       else
        {
          bitmap_clear_bit (curr_reg_live, regno);
-         curr_reg_pressure[cover_class]--;
+         curr_reg_pressure[(int) cover_class]--;
        }
     }
 }
@@ -1115,7 +1117,7 @@ 
   int i, change, before, after, hard_regno;
   int excess_cost_change;
   enum machine_mode mode;
-  enum reg_class cl;
+  reg_class_t cl;
   struct reg_pressure_data *pressure_info;
   int *max_reg_pressure;
   struct reg_use_data *use;
@@ -1130,10 +1132,11 @@ 
     if (dying_use_p (use))
       {
        cl = sched_regno_cover_class[use->regno];
-       if (use->regno < FIRST_PSEUDO_REGISTER)
-         death[cl]++;
+       if (HARD_REGISTER_NUM_P (use->regno))
+         death[(int) cl]++;
        else
-         death[cl] += ira_reg_class_nregs[cl][PSEUDO_REGNO_MODE (use->regno)];
+         death[(int) cl]
+           += ira_reg_class_nregs[(int) cl][PSEUDO_REGNO_MODE (use->regno)];
       }
   pressure_info = INSN_REG_PRESSURE (insn);
   max_reg_pressure = INSN_MAX_REG_PRESSURE (insn);
@@ -1141,17 +1144,17 @@ 
   for (i = 0; i < ira_reg_class_cover_size; i++)
     {
       cl = ira_reg_class_cover[i];
-      gcc_assert (curr_reg_pressure[cl] >= 0);
-      change = (int) pressure_info[i].set_increase - death[cl];
-      before = MAX (0, max_reg_pressure[i] - ira_available_class_regs[cl]);
+      gcc_assert (curr_reg_pressure[(int) cl] >= 0);
+      change = (int) pressure_info[i].set_increase - death[(int) cl];
+      before = MAX (0, max_reg_pressure[i] - ira_available_class_regs[(int) cl]);
       after = MAX (0, max_reg_pressure[i] + change
-                  - ira_available_class_regs[cl]);
-      hard_regno = ira_class_hard_regs[cl][0];
+                  - ira_available_class_regs[(int) cl]);
+      hard_regno = ira_class_hard_regs[(int) cl][0];
       gcc_assert (hard_regno >= 0);
       mode = reg_raw_mode[hard_regno];
       excess_cost_change += ((after - before)
-                            * (ira_memory_move_cost[mode][cl][0]
-                               + ira_memory_move_cost[mode][cl][1]));
+                            * (ira_memory_move_cost[mode][(int) cl][0]
+                               + ira_memory_move_cost[mode][(int) cl][1]));
     }
   INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insn) = excess_cost_change;
 }
@@ -3443,11 +3446,11 @@ 
 
       ira_set_pseudo_classes (sched_verbose ? sched_dump : NULL);
       sched_regno_cover_class
-       = (enum reg_class *) xmalloc (max_regno * sizeof (enum reg_class));
+       = (reg_class_t *) xmalloc (max_regno * sizeof (reg_class_t));
       for (i = 0; i < max_regno; i++)
        sched_regno_cover_class[i]
-         = (i < FIRST_PSEUDO_REGISTER
-            ? ira_class_translate[REGNO_REG_CLASS (i)]
+         = (HARD_REGISTER_NUM_P (i)
+            ? (reg_class_t) ira_class_translate[REGNO_REG_CLASS (i)]
             : reg_cover_class (i));
       curr_reg_live = BITMAP_ALLOC (NULL);
       saved_reg_live = BITMAP_ALLOC (NULL);
Index: gcc/ira-int.h
===================================================================
--- gcc/ira-int.h       (revision 166014)
+++ gcc/ira-int.h       (working copy)
@@ -960,8 +960,8 @@ 
 extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int,
                                        bool, rtx, ira_loop_tree_node_t);
 
-extern int *ira_allocate_cost_vector (enum reg_class);
-extern void ira_free_cost_vector (int *, enum reg_class);
+extern int *ira_allocate_cost_vector (reg_class_t);
+extern void ira_free_cost_vector (int *, reg_class_t);
 
 extern void ira_flattening (int, int);
 extern bool ira_build (bool);
@@ -1314,7 +1314,7 @@ 
 /* Allocate cost vector *VEC for hard registers of COVER_CLASS and
    initialize the elements by VAL if it is necessary */
 static inline void
-ira_allocate_and_set_costs (int **vec, enum reg_class cover_class, int val)
+ira_allocate_and_set_costs (int **vec, reg_class_t cover_class, int val)
 {
   int i, *reg_costs;
   int len;
@@ -1322,7 +1322,7 @@ 
   if (*vec != NULL)
     return;
   *vec = reg_costs = ira_allocate_cost_vector (cover_class);
-  len = ira_class_hard_regs_num[cover_class];
+  len = ira_class_hard_regs_num[(int) cover_class];
   for (i = 0; i < len; i++)
     reg_costs[i] = val;
 }
Index: gcc/regmove.c
===================================================================
--- gcc/regmove.c       (revision 166014)
+++ gcc/regmove.c       (working copy)
@@ -957,7 +957,7 @@ 
              rtx set, p, src, dst;
              rtx src_note, dst_note;
              int num_calls = 0, freq_calls = 0;
-             enum reg_class src_class, dst_class;
+             reg_class_t src_class, dst_class;
              int length;
 
              match_no = match.with[op_no];
Index: gcc/ira-build.c
===================================================================
--- gcc/ira-build.c     (revision 166014)
+++ gcc/ira-build.c     (working copy)
@@ -1390,17 +1390,17 @@ 
 
 /* Allocate and return a cost vector VEC for COVER_CLASS.  */
 int *
-ira_allocate_cost_vector (enum reg_class cover_class)
+ira_allocate_cost_vector (reg_class_t cover_class)
 {
-  return (int *) pool_alloc (cost_vector_pool[cover_class]);
+  return (int *) pool_alloc (cost_vector_pool[(int) cover_class]);
 }
 
 /* Free a cost vector VEC for COVER_CLASS.  */
 void
-ira_free_cost_vector (int *vec, enum reg_class cover_class)
+ira_free_cost_vector (int *vec, reg_class_t cover_class)
 {
   ira_assert (vec != NULL);
-  pool_free (cost_vector_pool[cover_class], vec);
+  pool_free (cost_vector_pool[(int) cover_class], vec);
 }
 
 /* Finish work with hard register cost vectors.  Release allocation
@@ -2943,20 +2943,20 @@ 
 
   FOR_EACH_ALLOCNO (a, ai)
     {
-      enum reg_class cover_class = ALLOCNO_COVER_CLASS (a);
-      enum reg_class pref = reg_preferred_class (ALLOCNO_REGNO (a));
+      reg_class_t cover_class = ALLOCNO_COVER_CLASS (a);
+      reg_class_t pref = reg_preferred_class (ALLOCNO_REGNO (a));
 
-      if (reg_class_size[pref] != 1)
+      if (reg_class_size[(int) pref] != 1)
        continue;
-      index = (ira_class_hard_reg_index[cover_class]
-              [ira_class_hard_regs[pref][0]]);
+      index = (ira_class_hard_reg_index[(int) cover_class]
+              [ira_class_hard_regs[(int) pref][0]]);
       if (index < 0)
        continue;
       if (ALLOCNO_CONFLICT_HARD_REG_COSTS (a) == NULL
          || ALLOCNO_HARD_REG_COSTS (a) == NULL)
        continue;
       min = INT_MAX;
-      for (i = ira_class_hard_regs_num[cover_class] - 1; i >= 0; i--)
+      for (i = ira_class_hard_regs_num[(int) cover_class] - 1; i >= 0; i--)
        if (ALLOCNO_HARD_REG_COSTS (a)[i] > ALLOCNO_COVER_CLASS_COST (a)
            && min > ALLOCNO_HARD_REG_COSTS (a)[i])
          min = ALLOCNO_HARD_REG_COSTS (a)[i];
Index: gcc/loop-invariant.c
===================================================================
--- gcc/loop-invariant.c        (revision 166014)
+++ gcc/loop-invariant.c        (working copy)
@@ -1014,11 +1014,11 @@ 
 
 /* Return cover class and number of hard registers (through *NREGS)
    for destination of INSN. */
-static enum reg_class
+static reg_class_t
 get_cover_class_and_nregs (rtx insn, int *nregs)
 {
   rtx reg;
-  enum reg_class cover_class;
+  reg_class_t cover_class;
   rtx set = single_set (insn);
 
   /* Considered invariant insns have only one set.  */
@@ -1039,7 +1039,8 @@ 
        cover_class = GENERAL_REGS;
       else
        cover_class = reg_cover_class (REGNO (reg));
-      *nregs = ira_reg_class_nregs[cover_class][GET_MODE (SET_SRC (set))];
+      *nregs
+        = ira_reg_class_nregs[(int) cover_class][GET_MODE (SET_SRC (set))];
     }
   return cover_class;
 }
@@ -1078,10 +1079,10 @@ 
   else
     {
       int nregs;
-      enum reg_class cover_class;
+      reg_class_t cover_class;
 
       cover_class = get_cover_class_and_nregs (inv->insn, &nregs);
-      regs_needed[cover_class] += nregs;
+      regs_needed[(int) cover_class] += nregs;
     }
 
   if (!inv->cheap_address
@@ -1151,10 +1152,10 @@ 
          else
            {
              int nregs;
-             enum reg_class cover_class;
+             reg_class_t cover_class;
 
              cover_class = get_cover_class_and_nregs (inv->insn, &nregs);
-             aregs_needed[cover_class] -= nregs;
+             aregs_needed[(int) cover_class] -= nregs;
            }
        }
 
@@ -1617,14 +1618,15 @@ 
 
 /* Return cover class and number of needed hard registers (through
    *NREGS) of register REGNO.  */
-static enum reg_class
+static reg_class_t
 get_regno_cover_class (int regno, int *nregs)
 {
-  if (regno >= FIRST_PSEUDO_REGISTER)
+  if (!HARD_REGISTER_NUM_P (regno))
     {
-      enum reg_class cover_class = reg_cover_class (regno);
+      reg_class_t cover_class = reg_cover_class (regno);
 
-      *nregs = ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
+      *nregs
+       = ira_reg_class_nregs[(int) cover_class][PSEUDO_REGNO_MODE (regno)];
       return cover_class;
     }
   else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)
@@ -1646,18 +1648,18 @@ 
 change_pressure (int regno, bool incr_p)
 {
   int nregs;
-  enum reg_class cover_class;
+  reg_class_t cover_class;
 
   cover_class = get_regno_cover_class (regno, &nregs);
   if (! incr_p)
-    curr_reg_pressure[cover_class] -= nregs;
+    curr_reg_pressure[(int) cover_class] -= nregs;
   else
     {
-      curr_reg_pressure[cover_class] += nregs;
-      if (LOOP_DATA (curr_loop)->max_reg_pressure[cover_class]
-         < curr_reg_pressure[cover_class])
-       LOOP_DATA (curr_loop)->max_reg_pressure[cover_class]
-         = curr_reg_pressure[cover_class];
+      curr_reg_pressure[(int) cover_class] += nregs;
+      if (LOOP_DATA (curr_loop)->max_reg_pressure[(int) cover_class]
+         < curr_reg_pressure[(int) cover_class])
+       LOOP_DATA (curr_loop)->max_reg_pressure[(int) cover_class]
+         = curr_reg_pressure[(int) cover_class];
     }
 }
 
@@ -1864,11 +1866,11 @@ 
        EXECUTE_IF_SET_IN_BITMAP (&LOOP_DATA (loop)->regs_live, 0, j, bi)
          if (! bitmap_bit_p (&LOOP_DATA (loop)->regs_ref, j))
            {
-             enum reg_class cover_class;
+             reg_class_t cover_class;
              int nregs;
 
              cover_class = get_regno_cover_class (j, &nregs);
-             LOOP_DATA (loop)->max_reg_pressure[cover_class] -= nregs;
+             LOOP_DATA (loop)->max_reg_pressure[(int) cover_class] -= nregs;
            }
       }
   if (dump_file == NULL)
Index: gcc/ira.c
===================================================================
--- gcc/ira.c   (revision 166014)
+++ gcc/ira.c   (working copy)
@@ -1241,21 +1241,21 @@ 
 {
   int x_regno, n, i;
   ira_allocno_t a;
-  enum reg_class pref;
+  reg_class_t pref;
 
   /* We only deal with pseudo regs.  */
-  if (! x || GET_CODE (x) != REG)
+  if (! x || ! REG_P (x))
     return false;
 
   x_regno = REGNO (x);
-  if (x_regno < FIRST_PSEUDO_REGISTER)
+  if (HARD_REGISTER_NUM_P (x_regno))
     return false;
 
   /* If the pseudo prefers REGNO explicitly, then do not consider
      REGNO a bad spill choice.  */
   pref = reg_preferred_class (x_regno);
-  if (reg_class_size[pref] == 1)
-    return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno);
+  if (reg_class_size[(int) pref] == 1)
+    return !TEST_HARD_REG_BIT (reg_class_contents[(int) pref], regno);
 
   /* If the pseudo conflicts with REGNO, then we consider REGNO a
      poor choice for a reload regno.  */
Index: gcc/sched-deps.c
===================================================================
--- gcc/sched-deps.c    (revision 166014)
+++ gcc/sched-deps.c    (working copy)
@@ -1823,29 +1823,29 @@ 
 mark_insn_pseudo_birth (rtx insn, int regno, bool clobber_p, bool unused_p)
 {
   int incr, new_incr;
-  enum reg_class cl;
+  reg_class_t cl;
 
-  gcc_assert (regno >= FIRST_PSEUDO_REGISTER);
+  gcc_assert (!HARD_REGISTER_NUM_P (regno));
   cl = sched_regno_cover_class[regno];
   if (cl != NO_REGS)
     {
-      incr = ira_reg_class_nregs[cl][PSEUDO_REGNO_MODE (regno)];
+      incr = ira_reg_class_nregs[(int) cl][PSEUDO_REGNO_MODE (regno)];
       if (clobber_p)
        {
-         new_incr = reg_pressure_info[cl].clobber_increase + incr;
-         reg_pressure_info[cl].clobber_increase = new_incr;
+         new_incr = reg_pressure_info[(int) cl].clobber_increase + incr;
+         reg_pressure_info[(int) cl].clobber_increase = new_incr;
        }
       else if (unused_p)
        {
-         new_incr = reg_pressure_info[cl].unused_set_increase + incr;
-         reg_pressure_info[cl].unused_set_increase = new_incr;
+         new_incr = reg_pressure_info[(int) cl].unused_set_increase + incr;
+         reg_pressure_info[(int) cl].unused_set_increase = new_incr;
        }
       else
        {
-         new_incr = reg_pressure_info[cl].set_increase + incr;
-         reg_pressure_info[cl].set_increase = new_incr;
+         new_incr = reg_pressure_info[(int) cl].set_increase + incr;
+         reg_pressure_info[(int) cl].set_increase = new_incr;
          if (! insn_use_p (insn, regno))
-           reg_pressure_info[cl].change += incr;
+           reg_pressure_info[(int) cl].change += incr;
          create_insn_reg_set (regno, insn);
        }
       gcc_assert (new_incr < (1 << INCREASE_BITS));
@@ -1858,12 +1858,12 @@ 
 mark_insn_hard_regno_birth (rtx insn, int regno, int nregs,
                            bool clobber_p, bool unused_p)
 {
-  enum reg_class cl;
+  reg_class_t cl;
   int new_incr, last = regno + nregs;
 
   while (regno < last)
     {
-      gcc_assert (regno < FIRST_PSEUDO_REGISTER);
+      gcc_assert (HARD_REGISTER_NUM_P (regno));
       if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
        {
          cl = sched_regno_cover_class[regno];
@@ -1871,20 +1871,21 @@ 
            {
              if (clobber_p)
                {
-                 new_incr = reg_pressure_info[cl].clobber_increase + 1;
-                 reg_pressure_info[cl].clobber_increase = new_incr;
+                 new_incr = reg_pressure_info[(int) cl].clobber_increase + 1;
+                 reg_pressure_info[(int) cl].clobber_increase = new_incr;
                }
              else if (unused_p)
                {
-                 new_incr = reg_pressure_info[cl].unused_set_increase + 1;
-                 reg_pressure_info[cl].unused_set_increase = new_incr;
+                 new_incr
+                    = reg_pressure_info[(int) cl].unused_set_increase + 1;
+                 reg_pressure_info[(int) cl].unused_set_increase = new_incr;
                }
              else
                {
-                 new_incr = reg_pressure_info[cl].set_increase + 1;
-                 reg_pressure_info[cl].set_increase = new_incr;
+                 new_incr = reg_pressure_info[(int) cl].set_increase + 1;
+                 reg_pressure_info[(int) cl].set_increase = new_incr;
                  if (! insn_use_p (insn, regno))
-                   reg_pressure_info[cl].change += 1;
+                   reg_pressure_info[(int) cl].change += 1;
                  create_insn_reg_set (regno, insn);
                }
              gcc_assert (new_incr < (1 << INCREASE_BITS));
@@ -1924,14 +1925,14 @@ 
 mark_pseudo_death (int regno)
 {
   int incr;
-  enum reg_class cl;
+  reg_class_t cl;
 
-  gcc_assert (regno >= FIRST_PSEUDO_REGISTER);
+  gcc_assert (!HARD_REGISTER_NUM_P (regno));
   cl = sched_regno_cover_class[regno];
   if (cl != NO_REGS)
     {
-      incr = ira_reg_class_nregs[cl][PSEUDO_REGNO_MODE (regno)];
-      reg_pressure_info[cl].change -= incr;
+      incr = ira_reg_class_nregs[(int) cl][PSEUDO_REGNO_MODE (regno)];
+      reg_pressure_info[(int) cl].change -= incr;
     }
 }
 
@@ -1940,17 +1941,17 @@ 
 static void
 mark_hard_regno_death (int regno, int nregs)
 {
-  enum reg_class cl;
+  reg_class_t cl;
   int last = regno + nregs;
 
   while (regno < last)
     {
-      gcc_assert (regno < FIRST_PSEUDO_REGISTER);
+      gcc_assert (HARD_REGISTER_NUM_P (regno));
       if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
        {
          cl = sched_regno_cover_class[regno];
          if (cl != NO_REGS)
-           reg_pressure_info[cl].change -= 1;
+           reg_pressure_info[(int) cl].change -= 1;
        }
       regno++;
     }
Index: gcc/ira-costs.c
===================================================================
--- gcc/ira-costs.c     (revision 166014)
+++ gcc/ira-costs.c     (working copy)
@@ -1075,7 +1075,8 @@ 
   fprintf (f, "\n");
   FOR_EACH_ALLOCNO (a, ai)
     {
-      int i, rclass;
+      int i;
+      reg_class_t rclass;
       basic_block bb;
       int regno = ALLOCNO_REGNO (a);
 
@@ -1089,17 +1090,17 @@ 
       for (k = 0; k < cost_classes_num; k++)
        {
          rclass = cost_classes[k];
-         if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)]
+         if (contains_reg_of_mode[(int) rclass][PSEUDO_REGNO_MODE (regno)]
 #ifdef FORBIDDEN_INC_DEC_CLASSES
-             && (! in_inc_dec[i] || ! forbidden_inc_dec_class[rclass])
+             && (! in_inc_dec[i] || ! forbidden_inc_dec_class[(int) rclass])
 #endif
 #ifdef CANNOT_CHANGE_MODE_CLASS
-             && ! invalid_mode_change_p (regno, (enum reg_class) rclass,
+             && ! invalid_mode_change_p (regno, rclass,
                                          PSEUDO_REGNO_MODE (regno))
 #endif
              )
            {
-             fprintf (f, " %s:%d", reg_class_names[rclass],
+             fprintf (f, " %s:%d", reg_class_names[(int) rclass],
                       COSTS (costs, i)->cost[k]);
              if (flag_ira_region == IRA_REGION_ALL
                  || flag_ira_region == IRA_REGION_MIXED)
@@ -1115,7 +1116,7 @@ 
 print_pseudo_costs (FILE *f)
 {
   int regno, k;
-  int rclass;
+  reg_class_t rclass;
 
   ira_assert (! allocno_p);
   fprintf (f, "\n");
@@ -1127,16 +1128,16 @@ 
       for (k = 0; k < cost_classes_num; k++)
        {
          rclass = cost_classes[k];
-         if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)]
+         if (contains_reg_of_mode[(int) rclass][PSEUDO_REGNO_MODE (regno)]
 #ifdef FORBIDDEN_INC_DEC_CLASSES
-             && (! in_inc_dec[regno] || ! forbidden_inc_dec_class[rclass])
+             && (! in_inc_dec[regno] || ! forbidden_inc_dec_class[(int) rclass])
 #endif
 #ifdef CANNOT_CHANGE_MODE_CLASS
-             && ! invalid_mode_change_p (regno, (enum reg_class) rclass,
+             && ! invalid_mode_change_p (regno, rclass,
                                          PSEUDO_REGNO_MODE (regno))
 #endif
              )
-           fprintf (f, " %s:%d", reg_class_names[rclass],
+           fprintf (f, " %s:%d", reg_class_names[(int) rclass],
                     COSTS (costs, regno)->cost[k]);
        }
       fprintf (f, " MEM:%i\n", COSTS (costs, regno)->mem_cost);
@@ -1192,7 +1193,8 @@ 
 
       pref = pref_buffer;
       FOR_EACH_ALLOCNO (a, ai)
-       pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a));
+       pref[ALLOCNO_NUM (a)]
+         = (enum reg_class) reg_preferred_class (ALLOCNO_REGNO (a));
       if (flag_expensive_optimizations)
        start = 1;
     }
@@ -1257,7 +1259,8 @@ 
       for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
        {
          ira_allocno_t a, parent_a;
-         int rclass, a_num, parent_a_num;
+         reg_class_t rclass;
+         int a_num, parent_a_num;
          ira_loop_tree_node_t parent;
          int best_cost, allocno_cost;
          enum reg_class best, alt_class;
@@ -1332,13 +1335,12 @@ 
              rclass = cost_classes[k];
              /* Ignore classes that are too small for this operand or
                 invalid for an operand that was auto-incremented.  */
-             if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)]
+             if (! contains_reg_of_mode[(int) rclass][PSEUDO_REGNO_MODE (i)]
 #ifdef FORBIDDEN_INC_DEC_CLASSES
-                 || (inc_dec_p && forbidden_inc_dec_class[rclass])
+                 || (inc_dec_p && forbidden_inc_dec_class[(int) rclass])
 #endif
 #ifdef CANNOT_CHANGE_MODE_CLASS
-                 || invalid_mode_change_p (i, (enum reg_class) rclass,
-                                           PSEUDO_REGNO_MODE (i))
+                 || invalid_mode_change_p (i, rclass, PSEUDO_REGNO_MODE (i))
 #endif
                  )
                continue;
@@ -1348,12 +1350,12 @@ 
                  best = (enum reg_class) rclass;
                }
              else if (temp_costs->cost[k] == best_cost)
-               best = ira_reg_class_union[best][rclass];
+               best = ira_reg_class_union[best][(int) rclass];
              if (pass == flag_expensive_optimizations
                  && temp_costs->cost[k] < temp_costs->mem_cost
-                 && (reg_class_size[reg_class_subunion[alt_class][rclass]]
+                 && (reg_class_size[reg_class_subunion[alt_class][(int) rclass]]
                      > reg_class_size[alt_class]))
-               alt_class = reg_class_subunion[alt_class][rclass];
+               alt_class = reg_class_subunion[alt_class][(int) rclass];
            }
          alt_class = ira_class_translate[alt_class];
          if (best_cost > temp_costs->mem_cost)
@@ -1403,17 +1405,17 @@ 
                  for (k = 0; k < cost_classes_num; k++)
                    {
                      rclass = cost_classes[k];
-                     if (! ira_class_subset_p[rclass][regno_cover_class[i]])
+                     if (! ira_class_subset_p[(int) rclass][regno_cover_class[i]])
                        continue;
                      /* Ignore classes that are too small for this
                         operand or invalid for an operand that was
                         auto-incremented.  */
-                     if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)]
+                     if (! contains_reg_of_mode[(int) rclass][PSEUDO_REGNO_MODE (i)]
 #ifdef FORBIDDEN_INC_DEC_CLASSES
-                         || (inc_dec_p && forbidden_inc_dec_class[rclass])
+                         || (inc_dec_p && forbidden_inc_dec_class[(int) rclass])
 #endif
 #ifdef CANNOT_CHANGE_MODE_CLASS
-                         || invalid_mode_change_p (i, (enum reg_class) rclass,
+                         || invalid_mode_change_p (i, rclass,
                                                    PSEUDO_REGNO_MODE (i))
 #endif
                          )
@@ -1429,7 +1431,7 @@ 
                      else if (COSTS (total_allocno_costs, a_num)->cost[k]
                               == best_cost)
                        {
-                         best = ira_reg_class_union[best][rclass];
+                         best = ira_reg_class_union[best][(int) rclass];
                          allocno_cost
                            = MAX (allocno_cost, COSTS (costs, a_num)->cost[k]);
                        }
Index: gcc/rtl.h
===================================================================
--- gcc/rtl.h   (revision 166014)
+++ gcc/rtl.h   (working copy)
@@ -1990,11 +1990,10 @@ 
 extern const char *decode_asm_operands (rtx, rtx *, rtx **, const char **,
                                        enum machine_mode *, location_t *);
 
-extern enum reg_class reg_preferred_class (int);
-extern enum reg_class reg_alternate_class (int);
-extern enum reg_class reg_cover_class (int);
-extern void setup_reg_classes (int, enum reg_class, enum reg_class,
-                              enum reg_class);
+extern reg_class_t reg_preferred_class (int);
+extern reg_class_t reg_alternate_class (int);
+extern reg_class_t reg_cover_class (int);
+extern void setup_reg_classes (int, reg_class_t, reg_class_t, reg_class_t);
 
 extern void split_all_insns (void);
 extern unsigned int split_all_insns_noflow (void);
@@ -2457,7 +2456,7 @@ 
 extern void regclass (rtx, int);
 extern void reg_scan (rtx, unsigned int);
 extern void fix_register (const char *, int, int);
-extern bool invalid_mode_change_p (unsigned int, enum reg_class,
+extern bool invalid_mode_change_p (unsigned int, reg_class_t,
                                   enum machine_mode);
 
 /* In reorg.c */
Index: gcc/sched-int.h
===================================================================
--- gcc/sched-int.h     (revision 166014)
+++ gcc/sched-int.h     (working copy)
@@ -655,7 +655,7 @@ 
 
 /* Map regno -> its cover class.  The map defined only when
    SCHED_PRESSURE_P is true.  */
-extern enum reg_class *sched_regno_cover_class;
+extern reg_class_t *sched_regno_cover_class;
 
 /* Indexed by INSN_UID, the collection of all data associated with
    a single instruction.  */
Index: gcc/reginfo.c
===================================================================
--- gcc/reginfo.c       (revision 166014)
+++ gcc/reginfo.c       (working copy)
@@ -848,9 +848,9 @@ 
 /* Structure used to record preferences of given pseudo.  */
 struct reg_pref
 {
-  /* (enum reg_class) prefclass is the preferred class.  May be
+  /* prefclass is the preferred class.  May be
      NO_REGS if no class is better than memory.  */
-  char prefclass;
+  reg_class_t prefclass;
 
   /* altclass is a register class that we should use for allocating
      pseudo if no register in the preferred class is available.
@@ -859,11 +859,11 @@ 
      It might appear to be more general to have a bitmask of classes here,
      but since it is recommended that there be a class corresponding to the
      union of most major pair of classes, that generality is not required.  */
-  char altclass;
+  reg_class_t altclass;
 
   /* coverclass is a register class that IRA uses for allocating
      the pseudo.  */
-  char coverclass;
+  reg_class_t coverclass;
 };
 
 /* Record preferences of each pseudo.  This is available after RA is
@@ -873,35 +873,35 @@ 
 /* Current size of reg_info.  */
 static int reg_info_size;
 
-/* Return the reg_class in which pseudo reg number REGNO is best allocated.
+/* Return the reg_class_t in which pseudo reg number REGNO is best allocated.
    This function is sometimes called before the info has been computed.
    When that happens, just return GENERAL_REGS, which is innocuous.  */
-enum reg_class
+reg_class_t
 reg_preferred_class (int regno)
 {
   if (reg_pref == 0)
     return GENERAL_REGS;
 
-  return (enum reg_class) reg_pref[regno].prefclass;
+  return reg_pref[regno].prefclass;
 }
 
-enum reg_class
+reg_class_t
 reg_alternate_class (int regno)
 {
   if (reg_pref == 0)
     return ALL_REGS;
 
-  return (enum reg_class) reg_pref[regno].altclass;
+  return reg_pref[regno].altclass;
 }
 
 /* Return the reg_class which is used by IRA for its allocation.  */
-enum reg_class
+reg_class_t
 reg_cover_class (int regno)
 {
   if (reg_pref == 0)
     return NO_REGS;
 
-  return (enum reg_class) reg_pref[regno].coverclass;
+  return reg_pref[regno].coverclass;
 }
 
 
@@ -1001,8 +1001,8 @@ 
    PREFCLASS, ALTCLASS, and COVERCLASS.  */
 void
 setup_reg_classes (int regno,
-                  enum reg_class prefclass, enum reg_class altclass,
-                  enum reg_class coverclass)
+                  reg_class_t prefclass, reg_class_t altclass,
+                  reg_class_t coverclass)
 {
   if (reg_pref == NULL)
     return;
@@ -1309,7 +1309,7 @@ 
    mode.  */
 bool
 invalid_mode_change_p (unsigned int regno,
-                      enum reg_class rclass ATTRIBUTE_UNUSED,
+                      reg_class_t rclass ATTRIBUTE_UNUSED,
                       enum machine_mode from)
 {
   struct subregs_of_mode_node dummy, *node;
@@ -1326,7 +1326,8 @@ 
   mask = 1 << (regno & 7);
   for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
     if (node->modes[to] & mask)
-      if (CANNOT_CHANGE_MODE_CLASS (from, (enum machine_mode) to, rclass))
+      if (CANNOT_CHANGE_MODE_CLASS (from, (enum machine_mode) to,
+                                   (enum reg_class) rclass))
        return true;
 
   return false;