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A RA patch necessary for new Intel insns generation

Message ID 24bb0b52-2509-8937-82d7-bd9b7293acac@redhat.com
State New
Headers show

Commit Message

Vladimir Makarov Nov. 10, 2016, 5:11 p.m. UTC
Hi, the following patch is necessary for generation of new Intel insns 
requiring 4 aligned zmm regs.

Committed as rev. 242043.
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Patch

Index: ChangeLog
===================================================================
--- ChangeLog	(revision 242040)
+++ ChangeLog	(working copy)
@@ -1,3 +1,12 @@ 
+2016-11-10  Vladimir Makarov  <vmakarov@redhat.com>
+
+	* target.def (additional_allocno_class_p): New.
+	* hooks.h (hook_bool_reg_class_t_false): New prototype.
+	* hooks.c (hook_bool_reg_class_t_false): New.
+	* ira.c (setup_allocno_and_important_classes): Use the new hook.
+	* doc/tm.texi.in (TARGET_ADDITIONAL_ALLOCNO_CLASS_P): Add it.
+	* doc/tm.texi: Update.
+
 2016-11-10  Jason Merrill  <jason@redhat.com>
 
 	* gengtype.c (new_structure): Append to structures list.
Index: hooks.h
===================================================================
--- hooks.h	(revision 242040)
+++ hooks.h	(working copy)
@@ -55,6 +55,7 @@  extern bool hook_bool_rtx_insn_true (rtx
 extern bool hook_bool_rtx_false (rtx);
 extern bool hook_bool_rtx_insn_int_false (rtx_insn *, int);
 extern bool hook_bool_uintp_uintp_false (unsigned int *, unsigned int *);
+extern bool hook_bool_reg_class_t_false (reg_class_t regclass);
 extern bool hook_bool_rtx_mode_int_int_intp_bool_false (rtx, machine_mode,
 							int, int, int *, bool);
 extern bool hook_bool_tree_tree_false (tree, tree);
Index: hooks.c
===================================================================
--- hooks.c	(revision 242040)
+++ hooks.c	(working copy)
@@ -466,3 +466,11 @@  hook_bool_uint_uintp_false (unsigned int
 {
   return false;
 }
+
+/* Generic hook that takes a register class and returns false.  */
+bool
+hook_bool_reg_class_t_false (reg_class_t regclass ATTRIBUTE_UNUSED)
+{
+  return false;
+}
+
Index: target.def
===================================================================
--- target.def	(revision 242040)
+++ target.def	(working copy)
@@ -5029,6 +5029,18 @@  DEFHOOK
  reg_class_t, (reg_class_t, machine_mode),
  NULL)
 
+/* Determine an additional allocno class.  */
+DEFHOOK
+(additional_allocno_class_p,
+ "This hook should return @code{true} if given class of registers should\
+  be an allocno class in any way.  Usually RA uses only one register\
+  class from all classes containing the same register set.  In some\
+  complicated cases, you need to have two or more such classes as\
+  allocno ones for RA correct work.  Not defining this hook is\
+  equivalent to returning @code{false} for all inputs.",
+ bool, (reg_class_t),
+ hook_bool_reg_class_t_false)
+
 DEFHOOK
 (cstore_mode,
  "This hook defines the machine mode to use for the boolean result of\
Index: ira.c
===================================================================
--- ira.c	(revision 242040)
+++ ira.c	(working copy)
@@ -1012,7 +1012,7 @@  setup_allocno_and_important_classes (voi
 				    temp_hard_regset2))
 	    break;
 	}
-      if (j >= n)
+      if (j >= n || targetm.additional_allocno_class_p (i))
 	classes[n++] = (enum reg_class) i;
       else if (i == GENERAL_REGS)
 	/* Prefer general regs.  For i386 example, it means that
Index: doc/tm.texi.in
===================================================================
--- doc/tm.texi.in	(revision 242040)
+++ doc/tm.texi.in	(working copy)
@@ -2507,6 +2507,8 @@  value that the middle-end intended.
 
 @hook TARGET_SPILL_CLASS
 
+@hook TARGET_ADDITIONAL_ALLOCNO_CLASS_P
+
 @hook TARGET_CSTORE_MODE
 
 @hook TARGET_COMPUTE_PRESSURE_CLASSES
Index: doc/tm.texi
===================================================================
--- doc/tm.texi	(revision 242040)
+++ doc/tm.texi	(working copy)
@@ -2899,6 +2899,10 @@  addressing.
 This hook defines a class of registers which could be used for spilling  pseudos of the given mode and class, or @code{NO_REGS} if only memory  should be used.  Not defining this hook is equivalent to returning  @code{NO_REGS} for all inputs.
 @end deftypefn
 
+@deftypefn {Target Hook} bool TARGET_ADDITIONAL_ALLOCNO_CLASS_P (reg_class_t)
+This hook should return @code{true} if given class of registers should  be an allocno class in any way.  Usually RA uses only one register  class from all classes containing the same register set.  In some  complicated cases, you need to have two or more such classes as  allocno ones for RA correct work.  Not defining this hook is  equivalent to returning @code{false} for all inputs.
+@end deftypefn
+
 @deftypefn {Target Hook} machine_mode TARGET_CSTORE_MODE (enum insn_code @var{icode})
 This hook defines the machine mode to use for the boolean result of  conditional store patterns.  The ICODE argument is the instruction code  for the cstore being performed.  Not definiting this hook is the same  as accepting the mode encoded into operand 0 of the cstore expander  patterns.
 @end deftypefn