From patchwork Wed Nov 9 13:09:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 692769 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tDRpF3FNpz9sdn for ; Thu, 10 Nov 2016 00:28:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753517AbcKIN2g (ORCPT ); Wed, 9 Nov 2016 08:28:36 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13634 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753831AbcKIN2d (ORCPT ); Wed, 9 Nov 2016 08:28:33 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 09 Nov 2016 05:44:47 -0800 Received: from HQMAIL101.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 09 Nov 2016 05:28:06 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 09 Nov 2016 05:28:06 -0800 Received: from DRUKMAIL102.nvidia.com (10.25.59.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 9 Nov 2016 13:25:54 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by drukmail102.nvidia.com (10.25.59.20) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 9 Nov 2016 13:25:49 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1210.3 via Frontend Transport; Wed, 9 Nov 2016 13:25:47 +0000 From: Laxman Dewangan To: , CC: , , , , Laxman Dewangan Subject: [PATCH V2 4/4] soc/tegra: pmc: Make configuration of IO pads in atomic context Date: Wed, 9 Nov 2016 18:39:22 +0530 Message-ID: <1478696962-11831-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1478696962-11831-1-git-send-email-ldewangan@nvidia.com> References: <1478696962-11831-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The IO pad voltage configuration can be done in the regulator notifier callback which is atomic in nature. Replace the mutex with spin lock for the locking mechanism. Signed-off-by: Laxman Dewangan --- Changes from V1: New in series based on pinctrl driver requirement. --- drivers/soc/tegra/pmc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 916a94b..52cd218 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -172,6 +172,7 @@ struct tegra_pmc_soc { * @lp0_vec_size: size of the LP0 warm boot code * @powergates_available: Bitmap of available power gates * @powergates_lock: mutex for power gate register access + * @io_pad_lock: Spinlock for IO pad voltage register access * @plat_subdevs: Platform device for PMC child devices. */ struct tegra_pmc { @@ -199,6 +200,7 @@ struct tegra_pmc { DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); struct mutex powergates_lock; + struct spinlock io_pad_lock; struct platform_device **plat_subdevs; }; @@ -1103,7 +1105,7 @@ int tegra_io_pad_set_voltage(enum tegra_io_pad id, if (pad->voltage == UINT_MAX) return -ENOTSUPP; - mutex_lock(&pmc->powergates_lock); + spin_lock(&pmc->io_pad_lock); /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ value = tegra_pmc_readl(PMC_PWR_DET); @@ -1120,7 +1122,7 @@ int tegra_io_pad_set_voltage(enum tegra_io_pad id, tegra_pmc_writel(value, PMC_PWR_DET_VALUE); - mutex_unlock(&pmc->powergates_lock); + spin_unlock(&pmc->io_pad_lock); usleep_range(100, 250); @@ -1800,6 +1802,7 @@ static int __init tegra_pmc_early_init(void) u32 value; mutex_init(&pmc->powergates_lock); + spin_lock_init(&pmc->io_pad_lock); np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); if (!np) {