| Message ID | 20161108143818.GA20524@linux.vnet.ibm.com |
|---|---|
| State | New |
| Headers | show |
On 08.11.2016 15:38, Dominik Vogt wrote: > The attached patch fixes PR/77822 on s390/s390x dor gcc-6 *only*. > See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77822 > > Bootstrapped and regression tested on s390 and s390x biarch on a > zEC12. missing the testcase mentioned in the ChangeLog.
On 11/08/2016 03:38 PM, Dominik Vogt wrote: > The attached patch fixes PR/77822 on s390/s390x dor gcc-6 *only*. > See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77822 > > Bootstrapped and regression tested on s390 and s390x biarch on a > zEC12. > > For gcc-7, there will be a different patch. Applied to GCC 6 branch. Thanks! Please remember adding the PR number to the changelog entries to trigger bugzilla adding a comment to the PR. As discussed offlist the range check for the position operand could be moved to a predicate. This will be part of the GCC head patch. I've just noticed that I had such checks already for the insv patterns and have added one to the expander as well later. So for zero_extract as target operand this appeared to be a problem even before GCC 6. Bye, -Andreas-
On 11.11.2016 09:58, Andreas Krebbel wrote: > On 11/08/2016 03:38 PM, Dominik Vogt wrote: >> The attached patch fixes PR/77822 on s390/s390x dor gcc-6 *only*. >> See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77822 >> >> Bootstrapped and regression tested on s390 and s390x biarch on a >> zEC12. >> >> For gcc-7, there will be a different patch. > > Applied to GCC 6 branch. Thanks! > Please remember adding the PR number to the changelog entries to trigger bugzilla adding a comment > to the PR. > > As discussed offlist the range check for the position operand could be moved to a predicate. This > will be part of the GCC head patch. > > I've just noticed that I had such checks already for the insv patterns and have added one to the > expander as well later. So for zero_extract as target operand this appeared to be a problem even > before GCC 6. the gcc-6-branch now has the ChangeLog entry for gcc.target/s390/pr77822.c but not the test case. Matthias
On 11/11/2016 10:42 AM, Matthias Klose wrote: > On 11.11.2016 09:58, Andreas Krebbel wrote: >> On 11/08/2016 03:38 PM, Dominik Vogt wrote: >>> The attached patch fixes PR/77822 on s390/s390x dor gcc-6 *only*. >>> See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77822 >>> >>> Bootstrapped and regression tested on s390 and s390x biarch on a >>> zEC12. >>> >>> For gcc-7, there will be a different patch. >> >> Applied to GCC 6 branch. Thanks! >> Please remember adding the PR number to the changelog entries to trigger bugzilla adding a comment >> to the PR. >> >> As discussed offlist the range check for the position operand could be moved to a predicate. This >> will be part of the GCC head patch. >> >> I've just noticed that I had such checks already for the insv patterns and have added one to the >> expander as well later. So for zero_extract as target operand this appeared to be a problem even >> before GCC 6. > > the gcc-6-branch now has the ChangeLog entry for gcc.target/s390/pr77822.c but > not the test case. > > Matthias > Fixed.
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index b3d4370..899ed62 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3708,6 +3708,10 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_Z10" { + if (!IN_RANGE (INTVAL (operands[3]), 0, GET_MODE_BITSIZE (DImode) - 1) + || !IN_RANGE (INTVAL (operands[3]) + INTVAL (operands[2]), 1, + GET_MODE_BITSIZE (DImode))) + FAIL; /* Starting with zEC12 there is risbgn not clobbering CC. */ if (TARGET_ZEC12) { @@ -3726,7 +3730,9 @@ (match_operand:GPR 1 "register_operand" "d") (match_operand 2 "const_int_operand" "") ; size (match_operand 3 "const_int_operand" "")))] ; start] - "TARGET_ZEC12" + "TARGET_ZEC12 + && IN_RANGE (INTVAL (operands[3]), 0, GET_MODE_BITSIZE (DImode) - 1) + && IN_RANGE (INTVAL (operands[3]) + INTVAL (operands[2]), 1, GET_MODE_BITSIZE (DImode))" "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift [(set_attr "op_type" "RIE")]) @@ -3737,7 +3743,9 @@ (match_operand 2 "const_int_operand" "") ; size (match_operand 3 "const_int_operand" ""))) ; start (clobber (reg:CC CC_REGNUM))] - "TARGET_Z10" + "TARGET_Z10 + && IN_RANGE (INTVAL (operands[3]), 0, GET_MODE_BITSIZE (DImode) - 1) + && IN_RANGE (INTVAL (operands[3]) + INTVAL (operands[2]), 1, GET_MODE_BITSIZE (DImode))" "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")])