@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
60000000 00407900 e0106a00 21046000
00000000 00000000 00000000 00038000
00000000 001b7200 00000000 00000000
@@ -2,13 +2,13 @@
aa55aa55 01ee0100
#enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
60000000 00407900 60040a00 21046000
00000000 00000000 00000000 00038000
00000000 001b7200 00000000 00000000
#disable IFC, enable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
#60000000 00407900 60040a00 21046000
#00000000 00000000 00000000 00038000
#20024800 001b7200 00000000 00000000
@@ -2,13 +2,13 @@
aa55aa55 01ee0100
#enable IFC, disable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
#60000000 00407900 60040a00 21046000
#00000000 00000000 00000000 00038000
#00000000 001b7200 00000000 00000000
#disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
60000000 00407900 60040a00 21046000
00000000 00000000 00000000 00038000
20024800 001b7200 00000000 00000000
@@ -2,7 +2,7 @@
aa55aa55 01ee0100
#enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
30000000 00007900 60040a00 21046000
00000000 00000000 00000000 20000000
00080000 881b7340 00000000 00000000
@@ -2,7 +2,7 @@
aa55aa55 01ee0100
#disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
30000000 00007900 60040a00 21046000
00000000 00000000 00000000 20000000
20024800 881b7340 00000000 00000000