diff mbox

[U-Boot,PATCHv2,3/3] igep00x0: add Hynix timings

Message ID 20161104115946.GC7713@localhost.localdomain
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Ladislav Michl Nov. 4, 2016, 11:59 a.m. UTC
Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and
Hynix H27S4G6F2DKA-BM

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---
Changes in v2:
 - None

Comments

Javier Martinez Canillas Nov. 4, 2016, 7:39 p.m. UTC | #1
Hello Ladis,

On Fri, Nov 4, 2016 at 8:59 AM, Ladislav Michl <ladis@linux-mips.org> wrote:
> Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and
> Hynix H27S4G6F2DKA-BM
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@samsung.com>

I don't have an IGEPv2 with Hynix to test, but everything is working
correctly on my IGEPv2 board with a Micron NAND.

Tested-by: Javier Martinez Canillas <javier@samsung.com>

Best regards,
Javier
Tom Rini Nov. 13, 2016, 8:58 p.m. UTC | #2
On Fri, Nov 04, 2016 at 12:59:46PM +0100, Ladislav Michl wrote:

> Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and
> Hynix H27S4G6F2DKA-BM
> 
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> Reviewed-by: Javier Martinez Canillas <javier@samsung.com>
> Tested-by: Javier Martinez Canillas <javier@samsung.com>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 71688cc..669f3dd 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -84,10 +84,22 @@  void get_board_mem_timings(struct board_sdrc_timings *timings)
 	int mfr, id, err = identify_nand_chip(&mfr, &id);
 
 	timings->mr = MICRON_V_MR_165;
-	if (!err && mfr == NAND_MFR_MICRON) {
-		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-		timings->ctrla = MICRON_V_ACTIMA_200;
-		timings->ctrlb = MICRON_V_ACTIMB_200;
+	if (!err) {
+		switch (mfr) {
+		case NAND_MFR_HYNIX:
+			timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+			timings->ctrla = HYNIX_V_ACTIMA_200;
+			timings->ctrlb = HYNIX_V_ACTIMB_200;
+			break;
+		case NAND_MFR_MICRON:
+			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_200;
+			timings->ctrlb = MICRON_V_ACTIMB_200;
+			break;
+		default:
+			/* Should not happen... */
+			break;
+		}
 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 	} else {