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[U-Boot,6/7] ARM: stm32: fix comment in stm32f7 header file

Message ID 1478037262-2044-7-git-send-email-michi.kurz@gmail.com
State Superseded
Headers show

Commit Message

Michael Kurz Nov. 1, 2016, 9:54 p.m. UTC 
This patch fixes a comment typo in stm32f7 rcc.h header

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
---

 arch/arm/include/asm/arch-stm32f7/rcc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
index dba6f23..64297ff 100644
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
@@ -22,7 +22,7 @@ 
 #define RCC_AHB3ENR	0x38	/* AHB3 peripheral clock enable */
 #define RCC_APB1ENR	0x40	/* APB1 peripheral clock enable */
 #define RCC_APB2ENR	0x44	/* APB2 peripheral clock enable */
-#define RCC_AHB1LPENR	0x50	/* periph clk enable in low pwr mode */
+#define RCC_AHB1LPENR	0x50	/* AHB1 periph clk enable in low pwr mode */
 #define RCC_AHB2LPENR	0x54	/* AHB2 periph clk enable in low pwr mode */
 #define RCC_AHB3LPENR	0x58	/* AHB3 periph clk enable in low pwr mode */
 #define RCC_APB1LPENR	0x60	/* APB1 periph clk enable in low pwr mode */