From patchwork Fri Oct 22 16:09:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [i386] : Fix PR target/46098 Date: Fri, 22 Oct 2010 06:09:08 -0000 From: Uros Bizjak X-Patchwork-Id: 68889 Message-Id: To: gcc-patches@gcc.gnu.org Hello! We have to fix mem/mem situation at expand time for unaligned moves. 2010-10-22 Uros Bizjak PR target/46098 * config/i386/sse.md (*avx_movu): Rename from avx_movu. (avx_movu): New expander. (*_movu): Rename from _movu. (_movu): New expander. (*avx_movdqu): Rename from avx_movdqu. (avx_movdqu): New expander. (*sse2_movdqu): Rename from sse2_movdqu. (sse2_movdqu): New expander. testsuite/ChangeLog: 2010-10-22 Uros Bizjak PR target/46098 * gcc.target/i386/pr46098.c: New test. Tested on x86_64-pc-linux-gnu, committed to 4.5 and mainline. Uros. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 165787) +++ config/i386/sse.md (working copy) @@ -382,7 +382,18 @@ DONE; }) -(define_insn "avx_movu" +(define_expand "avx_movu" + [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "") + (unspec:AVXMODEF2P + [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")] + UNSPEC_MOVU))] + "AVX_VEC_FLOAT_MODE_P (mode)" +{ + if (MEM_P (operands[0]) && MEM_P (operands[1])) + operands[1] = force_reg (mode, operands[1]); +}) + +(define_insn "*avx_movu" [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m") (unspec:AVXMODEF2P [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")] @@ -408,7 +419,18 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_insn "_movu" +(define_expand "_movu" + [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "") + (unspec:SSEMODEF2P + [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")] + UNSPEC_MOVU))] + "SSE_VEC_FLOAT_MODE_P (mode)" +{ + if (MEM_P (operands[0]) && MEM_P (operands[1])) + operands[1] = force_reg (mode, operands[1]); +}) + +(define_insn "*_movu" [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m") (unspec:SSEMODEF2P [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")] @@ -420,7 +442,18 @@ (set_attr "movu" "1") (set_attr "mode" "")]) -(define_insn "avx_movdqu" +(define_expand "avx_movdqu" + [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "") + (unspec:AVXMODEQI + [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")] + UNSPEC_MOVU))] + "TARGET_AVX" +{ + if (MEM_P (operands[0]) && MEM_P (operands[1])) + operands[1] = force_reg (mode, operands[1]); +}) + +(define_insn "*avx_movdqu" [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m") (unspec:AVXMODEQI [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")] @@ -432,7 +465,17 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "sse2_movdqu" +(define_expand "sse2_movdqu" + [(set (match_operand:V16QI 0 "nonimmediate_operand" "") + (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")] + UNSPEC_MOVU))] + "TARGET_SSE2" +{ + if (MEM_P (operands[0]) && MEM_P (operands[1])) + operands[1] = force_reg (V16QImode, operands[1]); +}) + +(define_insn "*sse2_movdqu" [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m") (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")] UNSPEC_MOVU))] Index: testsuite/gcc.target/i386/pr46098.c =================================================================== --- testsuite/gcc.target/i386/pr46098.c (revision 0) +++ testsuite/gcc.target/i386/pr46098.c (revision 0) @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -ffloat-store" } */ + +typedef double v2df __attribute__((vector_size (16))); + +v2df foo (double *d) +{ + return __builtin_ia32_loadupd (d); +}