===================================================================
@@ -382,7 +382,18 @@
DONE;
})
-(define_insn "avx_movu<ssemodesuffix><avxmodesuffix>"
+(define_expand "avx_movu<ssemodesuffix><avxmodesuffix>"
+ [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "")
+ (unspec:AVXMODEF2P
+ [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")]
+ UNSPEC_MOVU))]
+ "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
+{
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+})
+
+(define_insn "*avx_movu<ssemodesuffix><avxmodesuffix>"
[(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
(unspec:AVXMODEF2P
[(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
@@ -408,7 +419,18 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-(define_insn "<sse>_movu<ssemodesuffix>"
+(define_expand "<sse>_movu<ssemodesuffix>"
+ [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "")
+ (unspec:SSEMODEF2P
+ [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")]
+ UNSPEC_MOVU))]
+ "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+{
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+})
+
+(define_insn "*<sse>_movu<ssemodesuffix>"
[(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
(unspec:SSEMODEF2P
[(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
@@ -420,7 +442,18 @@
(set_attr "movu" "1")
(set_attr "mode" "<MODE>")])
-(define_insn "avx_movdqu<avxmodesuffix>"
+(define_expand "avx_movdqu<avxmodesuffix>"
+ [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "")
+ (unspec:AVXMODEQI
+ [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")]
+ UNSPEC_MOVU))]
+ "TARGET_AVX"
+{
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+})
+
+(define_insn "*avx_movdqu<avxmodesuffix>"
[(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
(unspec:AVXMODEQI
[(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
@@ -432,7 +465,17 @@
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
-(define_insn "sse2_movdqu"
+(define_expand "sse2_movdqu"
+ [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
+ (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")]
+ UNSPEC_MOVU))]
+ "TARGET_SSE2"
+{
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
+ operands[1] = force_reg (V16QImode, operands[1]);
+})
+
+(define_insn "*sse2_movdqu"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
(unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
UNSPEC_MOVU))]
===================================================================
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -ffloat-store" } */
+
+typedef double v2df __attribute__((vector_size (16)));
+
+v2df foo (double *d)
+{
+ return __builtin_ia32_loadupd (d);
+}